SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The HDQ1W module operates from two clocks: a functional clock (HDQ1W_FCLK) and an interface clock (HDQ1W_ICLK). When these clocks are set in the PRCM module, the following rule must be observed: HDQ1W_ICLK ≥ HDQ1W_FCLK.
For more information about the clock and the PRCM register settings, see CD_L4PER1 Clock Domain, in chapter Power, Reset, and Clock Management.
When the HDQ1W no longer requires the HDQ1W_FCLK, the software can disable it at the PRCM level. The clock is effectively cut, provided the other modules that receive it do not require it either.
When the HDQ1W no longer requires the HDQ1W_ICLK (no transfer is in progress), the software can disable it at the PRCM level. The clock is effectively cut, provided the other modules that receive it do not require it either.