The Cortex-A15 MPU subsystem integrates the following submodules:
- ARM Cortex-A15 MPCore
- Two central processing units (CPUs)
- ARM Version 7 ISA: Standard ARM instruction set plus
Thumb®-2,
Jazelle® RCT
Java™ accelerator, hardware virtualization support, and large physical address extensions (LPAE)
- Neon™ SIMD coprocessor and VFPv4 per CPU
- Interrupt controller with up to 160 interrupt requests
- One general-purpose timer and one watchdog timer per CPU
- Debug and trace features
- 32-KiB instruction and 32-KiB data level 1 (L1) cache per CPU
- Shared 2-MiB level 2 (L2) cache
- 48-KiB bootable ROM
- Local power, reset, and clock management (PRCM) module
- Emulation features
- Digital phase-locked loop (DPLL)