SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The EMIF Write Data FIFO and Command FIFO clocks are derived from the MPU clock (specifically, EMIF_MA_ICLK = MPU_GCLK/4) any time the MPU is active. As such, the DDR Peak Write bandwidth scales in proportion to the MPU clock frequency. At lower MPU clock frequencies (< 1 GHz), the Write Data FIFO limits writes to less than peak DDR bandwidth (assuming DDR3-1066 operating conditions.)
The SDRAM Read Data FIFO is always clocked by the EMIF_ICLK, so there is no relationship for read bandwidth relative to the MPU operating frequency.
The Command FIFO bandwidth is also controlled by the EMIF_MA_ICLK. However, because the command bandwidth is much lower than the data bandwidth, there is no visible bandwidth scaling for the command interface (and as a result, the read interface can be fully used).
The total available bandwidth is not affected for most systems. The write bandwidth is limited on an internal path, not on the DDR pins. The DDR pin bandwidth is still available for reads. Because most systems have higher bandwidth requirements for read relative to write, the available DDR bandwidth is still usable.