SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The EMIF module provides an interface to DDR2 and DDR3 SDRAM memories.
Figure 15-49 shows the interconnection between the EMIF module and the other modules.
Digital locked loops (DLLs) are used to delay the input DQS signals during reads so that these strobe signals can be used to latch incoming data on the DQ pins, as required by the DDR standard.
Physical layers (PHYs) convert single-data rate (SDR) signals to DDR signals.