SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The ARP32 CPU supports only little-endian byte ordering in the memory subsystem (see Figure 8-30). A word loaded from the memory is loaded into a CPU register as follows:
31 | 24 | 23 | 16 | 15 | 8 | 7 | 0 |
Word at address A | Byte [Addr + 3] | Byte [Addr + 2] | Byte [Addr + 1] | Byte [Addr + 0] | |||||||||||||||||||||||||||
Halfword at address A | Byte [Addr + 1] | Byte [Addr + 0] |