SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
When developing a table-based address translation scheme, one of the most important design parameters is the memory page size described by each translation table entry. MMU instances support 4-KiB and 64-KiB pages, a 1-MiB section, and a 16-MiB supersection. Using bigger page sizes means a smaller translation table.
Using a smaller page size greatly increases the efficiency of dynamic memory allocation and defragmentation. That is why many operating systems (OSs) can operate on memory blocks as small as 4 KiB; however, the smaller size implies a more complex table structure.
A quick calculation shows that using 4 KiB memory pages with one translation table would require one million entries to span the entire 4-GiB address range. The table itself would be 32 MiB, a size that is not feasible.
However, using bigger pages reduces the flexibility of typical OS memory management. Implementing a two-level hierarchy reconciles these two requirements. Within this hierarchy, one first-level translation table describes the translation properties based on 1 MiB memory regions.
Each of the entries in this first-level translation table can specify the following:
This hierarchical approach means that additional translation information for smaller pages must be provided only when the pages are actually used. Figure 20-7 shows the hierarchy.
The structure of the first and second-level translation tables and their entries are described in more detail in Section 20.3.1.2.2, First-Level Translation Table, and Section 20.3.1.2.3, Two-Level Translation.