SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The LCD outputs (LCD1, LCD2 and LCD3) can be configured in BT.656 or BT.1120 mode. The following standards are not supported in BT.656 mode:
Unsupported formats when BT.1120 mode is used:
BT.656/BT.1120 modes use embedded EAV/SAV syncs.
DISPC supports maximum 256 bytes of horizontal blanking when the LCD outputs are configured in BT modes (bitfield HSW of DISPC_TIMING_H1/2/3 registers is 8 bits wide). This is not compliant with BT.656 and BT.1120 standards, both of which require higher blanking periods. If more than 256 bytes of horizontal blanking are required by the application, then the RGB mode must be used for the LCD outputs.
Figure 11-85 shows signal mapping on DISPC_LCD_DATA[23:0] data bus. Bits 9 to 0 are used in BT.656 mode (10-bit).
For compatibility with existing 8-bit interfaces, the two LSB are ignored, and only bits [9:2] are used.
Figure 11-86 shows signal mapping on DISPC_LCD_DATA[23:0] data bus for BT.1120 mode. Bits [19:10] (CbCr) and [9:0] (Y) are used in 20-bit mode. Bits [19:12] (CbCr) and [9:2] (Y) are used in 16-bit mode (YCbCr 4:2:2).
The LCD outputs support both interlace and progressive content in BT.656/BT.1120 modes.
In progressive mode the maximum resolution will be limited, as it requires two clock cycles to send out one pixel.