SPRUI30H November 2015 – May 2024 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
This section provides recommended steps for initializing the DSS module.
Step | Register / Bit Field / Chapter | Value |
---|---|---|
Enable DSS clock domain | ||
Configure DPLL_PER and associated HS12 divider, according to the desired DSS_GFCLK frequency | Refer to Power, Reset, and Clock Management, section DPLL_PER Description | - |
Enable DES_HDCP clock | Set CTRL_CORE_CONTROL_IO_2[0] DSS_DESHDCP_CLKEN register bit; | 0x1 |
Refer to Control Module Register Manual | ||
Set SW wake-up transition for DSS clock domain | Set CM_DSS_CLKSTCTRL[1:0] CLKTRCTRL register bitfield; | 0x2 |
Refer to PRCM Register Manual | ||
Enable (ungate) DSS_GFCLK clock | Set CM_DSS_DSS_CLKCTRL[8] OPTFCLKEN_DSSCLK register bit; | 0x1 |
Refer to PRCM Register Manual | ||
Enable DSS clocks | Set CM_DSS_DSS_CLKCTRL[1:0] MODULEMODE register bitfield; | 0x2 |
Refer to PRCM Register Manual | ||
Wait for DSS idle status (functional or in idle mode) | Read CM_DSS_DSS_CLKCTRL[17:16] IDLEST register bit-field; | 0x0 or 0x2 |
Refer to PRCM Register Manual | ||
Make DSS DPLLs accessible via DSS address space | ||
Make VIDEO1, VIDEO2 and HDMI DPLLs accessible via DSS | Clear the following bits in CTRL_CORE_DSS_PLL_CONTROL register: | 0x0 |
[2] PLL_HDMI_DSS_CONTROL_DISABLE bit; | ||
[1] PLL_VIDEO2_DSS_CONTROL_DISABLE bit; | ||
[0] PLL_VIDEO1_DSS_CONTROL_DISABLE bit; | ||
Refer to Control Module Register Manual | ||
Enable DSS internal SCP interface | ||
Enable DSS internal SCP interface for VIDEO1 and VIDEO2 DPLL register configuration | Set DSI_CLK_CTRL[14] CIO_CLK_ICG register bit | 0x1 |
Configure DSS internal SCP interface for HDMI DPLL register configuration | Set HDMI_WP_CLK[ 10:8] SCP_PWR_DIV register bit-field | 0x- |
Configure DSS DPLLs | ||
Enable (ungate) VIDEO1, VIDEO2 and HDMI DPLLs source clocks | Set the following bits in CM_DSS_DSS_CLKCTRL register: | 0x1 |
[13] OPTFCLKEN_VIDEO2_CLK bit; | ||
[12] OPTFCLKEN_VIDEO1_CLK bit; | ||
[10] OPTFCLKEN_HDMI_CLK bit; | ||
Refer to PRCM Register Manual | ||
Proceed with VIDEO1, VIDEO2 and HDMI DPLLs configuration | Refer to Display Subsystem DPLL Controllers Functional Description | - |