SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
TR pipelining refers to the ability of the source active set to proceed ahead of the destination active set. Essentially, the reads for a given TR may already be in progress while the writes of a previous TR may not have completed.
The number of outstanding TRs is limited by the number of destination FIFO register entries.
TR pipelining is useful for maintaining throughput on back-to-back small TRs. It minimizes the startup overhead because reads start in the background of a previous TR writes.