SPRUI30H November 2015 – May 2024 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
The device operation requires external input clocks, as follows:
The device provides wide choice of clocks that can be delivered on clkout[1:3] pads to companion devices. For more information, see Section 3.3, PRCM Subsystem Environment, in Chapter 3, Power, Reset, and Clock Management. For more information on pad multiplexing, see Chapter 18, Control Module.
Table 32-2 lists the mapping for the device clock input sources. Table 32-3 lists the PMIC clock requirements.
Clock | Clock Source | Ball Mapping | Frequency Range/List | Type |
---|---|---|---|---|
SYS_CLK1 | Internal oscillator 0 (OSC0) | xi_osc0 and xo_osc0 | 19.2, 20, and 27 MHz | Crystal connection pins |
External | xi_osc0 | 19.2, 20, and 27 MHz | External LVCMOS | |
SYS_CLK2 | Internal oscillator 1 (OSC1) | xi_osc1 and xo_osc1 | 19.2 ÷ 32 MHz | Crystal connection pins |
External | xi_osc1 | 12 ÷ 38.4 MHz | External LVCMOS |
Clock Source(1) | Mapping | Frequency Range/List | Type |
---|---|---|---|
Internal oscillator | OSC16MIN and OSC16MOUT | 16.384 MHz | Crystal connection pins |
External | OSC16MIN | 32.768 kHz (nom.) | External LVCMOS |
Clock configurations depend on core voltage, and maximum clock frequencies may not apply to production. For more information, see the Device Data Manual.