The main features of the watchdog timer controllers are:
- L4 slave interface support:
- 32-bit data bus width
- 32-/16-bit access supported
- 8-bit access not supported
- 11-bit address bus width
- Burst mode not supported
- Write nonposted mode supported
- Free-running 32-bit upward counter
- Programmable divider clock source (2n where n = [0:7])
- On-the-fly read/write register (while counting)
- Subset programming model of the GP timer
- The watchdog timer is reset either on power on or after a warm reset before it starts counting.
- Reset or interrupt actions when a timer overflow condition occurs
- The watchdog timer generates a reset or an interrupt in its hardware integration.