The PCIe controller slave port gives access to two internal targets: the local target, to manage the local controller, and the outbound window, which forwards accesses onto the PCIe wire.
The PCIe slave port (using AXI protocol with an adapter to the device L3_MAIN interconnect) has the following key features:
- 64-bit data, 29-bit address bus width
- Up to 16 simultaneous outstanding transactions, up to 16 different IDs (4-bit ID port).
- Uses the same clock source as the PCIe controller master port, but potentially on a different divider ratio.
- Supports L3_MAIN disconnect protocol
- Exclusive and locked accesses are not supported for read and write port
PCIe Controller slave port purposes are:
- Configuration and management of the PCIe controller:
- This low-bandwidth activity accesses the device PCIe controller local configuration/status registers, the Port Logic registers and the PCIe controller wrapper TI-specific registers.
- The L3_MAIN base address corresponding to the PCIe_SS1 controller local configuration/status registers (DIF access targets) is 0x5100_0000. For the PCIe_SS2 controller local configuration/status registers (DIF access targets), the L3_MAIN base address is 0x5180_0000.
- Bursts are not supported when accessing these registers.
- Outbound PCIe traffic:
- This activity can consume the entire bandwidth available on the PCIe wires (up to 1 Gbyte/s in each direction for 2-lane, Gen2 operation), in concurrence with the AXI master ports’ operation (that carries inbound PCIe traffic).
- PCIe controller maximum outbound payload size is 64 Bytes (the L3 Interconnect PCIe1/2 target ports split bursts of size > 64 Bytes to the into multiple 64 Byte bursts). Only bursts of incremental type (INCR) are supported on the PCIe controller slave port.
- Non-aligned bursts can be generated.
- All outbound traffic activities are mapped within a device L3_MAIN space region which is 256 MiB in size.
- For the PCIe_SS1 controller the PCIe outbound window is mapped within range 0x2000_0000 - 0x2FFF_FFFF of the device L3_MAIN memory space. For the PCIe_SS2 controller the PCIe outbound window is mapped within range 0x3000_0000 - 0x3FFF_FFFF (256 MiB) of the device L3_MAIN memory space.
Note: The PCIe controller remains fully functional, and able to send transactions to, for example, anywhere within the 64-bit PCIe memory space, with the appropriate remapping of the 28-bit address by the outbound address translation unit (iATU). The limitation is that the total size of addressed PCIe regions (in config, memory, IO spaces) must be less than 228 bytes.