SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
Before PCI enumeration, each BAR can be initialized/enabled individually for IO space, using the DIF access (CS or CS2). The size of an enabled IO BAR (that is, the number of writable bits in the base address) is fixed to 256 bytes, that is, a mask of 0xFF that is, the writable BAR base address range for the RC is BARn[31:8], while BARn[7:0] is read-only.
In (CS) access, the BARn[0] "space decoder" field becomes RW and shall be written to 1 = IO space
In (CS2) access, BARn[0] becomes a write-only BAR enable :