SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The OCM controller generates two interrupt requests, OCMC_RAMi_IRQ and OCMC_RAMi_IRQ_CBUF (i = 1, 2 and 3. i depends on the device part number).
The OCMC_RAMi_IRQ line is associated with the following registers:
The OCMC_RAMi_IRQ_CBUF line is associated with the following registers:
Both the register groups previously described have identical bits. When for example, only one event occurs one or the two IRQ lines will be asserted depending on the masks applied to the INTR0_ENABLE_SET and INTR1_ENABLE_SET registers. When for example, a short frame detection event occurs and if both the INTR0_ENABLE_SET[14] CBUF_SHORT_FRAME_DETECT_FOUND and INTR1_ENABLE_SET[14] CBUF_SHORT_FRAME_DETECT_FOUND bits are set to 0x1, then both the OCMC_RAMi_IRQ and OCMC_RAMi_IRQ_CBUF lines are asserted. If only the INTR0_ENABLE_SET[14] CBUF_SHORT_FRAME_DETECT_FOUND bit is set to 0x1, then only the OCMC_RAMi_IRQ line is asserted and the OCMC_RAMi_IRQ_CBUF line remains inactive (deasserted). Thus depending on the mask applied one IRQ line of the OCM controller can be associated only with CBUF events for example, and the other one IRQ line can be associated with ECC events. In other words, two unique interrupts can be provided.
Table 15-556 lists the interrupt events which can assert the two interrupt lines of the OCM controller.
The OCM controller asserts each of its interrupt lines only if the interrupts are enabled by setting to 0x1 the corresponding bits in the INTR0_ENABLE_SET/INTR1_ENABLE_SET register. These interrupts can be disabled by setting to 0x1 the corresponding bits in the INTR0_ENABLE_CLEAR/INTR1_ENABLE_CLEAR register. After the interrupt has been serviced the corresponding status flag must be cleared by software. This is done by setting to 0x1 the corresponding bit in the INTR0_STATUS_ENABLED_CLEAR/INTR1_STATUS_ENABLED_CLEAR register which also clears the corresponding bit in the INTR0_STATUS_RAW_SET/INTR1_STATUS_RAW_SET register. The status flags in the INTR0_STATUS_RAW_SET/INTR1_STATUS_RAW_SET register are set even if the corresponding interrupt is disabled as opposed to those in the INTR0_STATUS_ENABLED_CLEAR/INTR1_STATUS_ENABLED_CLEAR register, which are set only if the corresponding interrupt is enabled. An interrupt is also generated by the OCM controller, if certain bit in the INTR0_STATUS_RAW_SET/INTR1_STATUS_RAW_SET register is set to 0x1 and the corresponding interrupt is enabled through the INTR0_ENABLE_SET/INTR1_ENABLE_SET register. This is useful when user software debugging is performed. Additionally, even if interrupts are not enabled, certain status bit in the INTR0_STATUS_RAW_SET/INTR1_STATUS_RAW_SET register can be cleared by setting to 0x1 the corresponding bit in the INTR0_STATUS_ENABLED_CLEAR/INTR1_STATUS_ENABLED_CLEAR register.
For additional details regarding the CBUF related events, see Section 15.6.3.11, CBUF Mode Error Handling.
Event Flag | Event Mask | Description |
---|---|---|
INTR0_STATUS_RAW_SET[14] CBUF_SHORT_FRAME_DETECT_FOUND/INTR1_STATUS_RAW_SET[14] CBUF_SHORT_FRAME_DETECT_FOUND andINTR0_STATUS_ENABLED_CLEAR[14] CBUF_SHORT_FRAME_DETECT_FOUND/INTR1_STATUS_ENABLED_CLEAR[14] CBUF_SHORT_FRAME_DETECT_FOUND | INTR0_ENABLE_SET[14] CBUF_SHORT_FRAME_DETECT_FOUND/INTR1_ENABLE_SET[14] CBUF_SHORT_FRAME_DETECT_FOUND andINTR0_ENABLE_CLEAR[14] CBUF_SHORT_FRAME_DETECT_FOUND/INTR1_ENABLE_CLEAR[14] CBUF_SHORT_FRAME_DETECT_FOUND | This bit indicates a short frame detection. It is set if at least one of the bits in the STATUS_CBUF_SHORT_FRAME_DETECT register is set to 0x1. |
INTR0_STATUS_RAW_SET[13] CBUF_UNDERFLOW_ERR_FOUND/INTR1_STATUS_RAW_SET[13] CBUF_UNDERFLOW_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[13] CBUF_UNDERFLOW_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[13] CBUF_UNDERFLOW_ERR_FOUND | INTR0_ENABLE_SET[13] CBUF_UNDERFLOW_ERR_FOUND/INTR1_ENABLE_SET[13] CBUF_UNDERFLOW_ERR_FOUND andINTR0_ENABLE_CLEAR[13] CBUF_UNDERFLOW_ERR_FOUND/INTR1_ENABLE_CLEAR[13] CBUF_UNDERFLOW_ERR_FOUND | Indicates CBUF underflow detction. This bit is set if at least one of the bits in the STATUS_CBUF_UNDERFLOW register is set to 0x1. |
INTR0_STATUS_RAW_SET[12] CBUF_OVERFLOW_WRAP_ERR_FOUND/INTR1_STATUS_RAW_SET[12] CBUF_OVERFLOW_WRAP_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[12] CBUF_OVERFLOW_WRAP_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[12] CBUF_OVERFLOW_WRAP_ERR_FOUND | INTR0_ENABLE_SET[12] CBUF_OVERFLOW_WRAP_ERR_FOUND/INTR1_ENABLE_SET[12] CBUF_OVERFLOW_WRAP_ERR_FOUND andINTR0_ENABLE_CLEAR[12] CBUF_OVERFLOW_WRAP_ERR_FOUND/INTR1_ENABLE_CLEAR[12] CBUF_OVERFLOW_WRAP_ERR_FOUND | Indicates Cbuf_Overflow_Wrap event |
INTR0_STATUS_RAW_SET[11] CBUF_OVERFLOW_MID_ERR_FOUND/INTR1_STATUS_RAW_SET[11] CBUF_OVERFLOW_MID_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[11] CBUF_OVERFLOW_MID_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[11] CBUF_OVERFLOW_MID_ERR_FOUND | INTR0_ENABLE_SET[11] CBUF_OVERFLOW_MID_ERR_FOUND/INTR1_ENABLE_SET[11] CBUF_OVERFLOW_MID_ERR_FOUND andINTR0_ENABLE_CLEAR[11] CBUF_OVERFLOW_MID_ERR_FOUND/INTR1_ENABLE_CLEAR[11] CBUF_OVERFLOW_MID_ERR_FOUND | Indicates Cbuf_Overflow_Mid event |
INTR0_STATUS_RAW_SET[10] CBUF_READ_SEQUENCE_ERR_FOUND/INTR1_STATUS_RAW_SET[10] CBUF_READ_SEQUENCE_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[10] CBUF_READ_SEQUENCE_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[10] CBUF_READ_SEQUENCE_ERR_FOUND | INTR0_ENABLE_SET[10] CBUF_READ_SEQUENCE_ERR_FOUND/INTR1_ENABLE_SET[10] CBUF_READ_SEQUENCE_ERR_FOUND andINTR0_ENABLE_CLEAR[10] CBUF_READ_SEQUENCE_ERR_FOUND/INTR1_ENABLE_CLEAR[10] CBUF_READ_SEQUENCE_ERR_FOUND | This flag indicates that at least one CBUF read address is not incrementing in raster scan order(1). |
INTR0_STATUS_RAW_SET[9] CBUF_VBUF_READ_START_ERR_FOUND/INTR1_STATUS_RAW_SET[9] CBUF_VBUF_READ_START_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[9] CBUF_VBUF_READ_START_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[9] CBUF_VBUF_READ_START_ERR_FOUND | INTR0_ENABLE_SET[9] CBUF_VBUF_READ_START_ERR_FOUND/INTR1_ENABLE_SET[9] CBUF_VBUF_READ_START_ERR_FOUND andINTR0_ENABLE_CLEAR[9] CBUF_VBUF_READ_START_ERR_FOUND/INTR1_ENABLE_CLEAR[9] CBUF_VBUF_READ_START_ERR_FOUND | This flag indicates when at least one of the CBUF read accesses does not start at the VBUF start address(1). |
INTR0_STATUS_RAW_SET[8] CBUF_READ_OUT_OF_RANGE_ERR_FOUND/INTR1_STATUS_RAW_SET[8] CBUF_READ_OUT_OF_RANGE_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[8] CBUF_READ_OUT_OF_RANGE_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[8] CBUF_READ_OUT_OF_RANGE_ERR_FOUND | INTR0_ENABLE_SET[8] CBUF_READ_OUT_OF_RANGE_ERR_FOUND/INTR1_ENABLE_SET[8] CBUF_READ_OUT_OF_RANGE_ERR_FOUND andINTR0_ENABLE_CLEAR[8] CBUF_READ_OUT_OF_RANGE_ERR_FOUND/INTR1_ENABLE_CLEAR[8] CBUF_READ_OUT_OF_RANGE_ERR_FOUND | This flag indicates when at least one of the CBUF read addresses is out of the CBUF address range(1). |
INTR0_STATUS_RAW_SET[7] CBUF_WRITE_SEQUENCE_ERR_FOUND/INTR1_STATUS_RAW_SET[7] CBUF_WRITE_SEQUENCE_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[7] CBUF_WRITE_SEQUENCE_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[7] CBUF_WRITE_SEQUENCE_ERR_FOUND | INTR0_ENABLE_SET[7] CBUF_WRITE_SEQUENCE_ERR_FOUND/INTR1_ENABLE_SET[7] CBUF_WRITE_SEQUENCE_ERR_FOUND andINTR0_ENABLE_CLEAR[7] CBUF_WRITE_SEQUENCE_ERR_FOUND/INTR1_ENABLE_CLEAR[7] CBUF_WRITE_SEQUENCE_ERR_FOUND | This flag indicates that at least one CBUF write address is not incrementing in raster scan order(1). |
INTR0_STATUS_RAW_SET[6] CBUF_VBUF_WRITE_START_ERR_FOUND/INTR1_STATUS_RAW_SET[6] CBUF_VBUF_WRITE_START_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[6] CBUF_VBUF_WRITE_START_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[6] CBUF_VBUF_WRITE_START_ERR_FOUND | INTR0_ENABLE_SET[6] CBUF_VBUF_WRITE_START_ERR_FOUND/INTR1_ENABLE_SET[6] CBUF_VBUF_WRITE_START_ERR_FOUND andINTR0_ENABLE_CLEAR[6] CBUF_VBUF_WRITE_START_ERR_FOUND/INTR1_ENABLE_CLEAR[6] CBUF_VBUF_WRITE_START_ERR_FOUND | This flag indicates when at least one of the CBUF write accesses does not start at the VBUF start address(1). |
INTR0_STATUS_RAW_SET[5] CBUF_WR_OUT_OF_RANGE_ERR_FOUND/INTR1_STATUS_RAW_SET[5] CBUF_WR_OUT_OF_RANGE_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[5] CBUF_WR_OUT_OF_RANGE_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[5] CBUF_WR_OUT_OF_RANGE_ERR_FOUND | INTR0_ENABLE_SET[5] CBUF_WR_OUT_OF_RANGE_ERR_FOUND/INTR1_ENABLE_SET[5] CBUF_WR_OUT_OF_RANGE_ERR_FOUND andINTR0_ENABLE_CLEAR[5] CBUF_WR_OUT_OF_RANGE_ERR_FOUND/INTR1_ENABLE_CLEAR[5] CBUF_WR_OUT_OF_RANGE_ERR_FOUND | This flag indicates when at least one of the CBUF write addresses is out of the CBUF address range(1). |
INTR0_STATUS_RAW_SET[4] CBUF_VIRTUAL_ADDR_ERR_FOUND/INTR1_STATUS_RAW_SET[4] CBUF_VIRTUAL_ADDR_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[4] CBUF_VIRTUAL_ADDR_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[4] CBUF_VIRTUAL_ADDR_ERR_FOUND | INTR0_ENABLE_SET[4] CBUF_VIRTUAL_ADDR_ERR_FOUND/INTR1_ENABLE_SET[4] CBUF_VIRTUAL_ADDR_ERR_FOUND andINTR0_ENABLE_CLEAR[4] CBUF_VIRTUAL_ADDR_ERR_FOUND/INTR1_ENABLE_CLEAR[4] CBUF_VIRTUAL_ADDR_ERR_FOUND | This flag indicates when a virtual address error is detected. This is a general interrupt event which is not associated with any specific CBUF(1). |
INTR0_STATUS_RAW_SET[3] OUT_OF_RANGE_ERR_FOUND/INTR1_STATUS_RAW_SET[3] OUT_OF_RANGE_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[3] OUT_OF_RANGE_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[3] OUT_OF_RANGE_ERR_FOUND | INTR0_ENABLE_SET[3] OUT_OF_RANGE_ERR_FOUND/INTR1_ENABLE_SET[3] OUT_OF_RANGE_ERR_FOUND andINTR0_ENABLE_CLEAR[3] OUT_OF_RANGE_ERR_FOUND/INTR1_ENABLE_CLEAR[3] OUT_OF_RANGE_ERR_FOUND | General interrupt for an access made with illegal VBUF address(1). |
INTR0_STATUS_RAW_SET[2] ADDR_ERR_FOUND/INTR1_STATUS_RAW_SET[2] ADDR_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[2] ADDR_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[2] ADDR_ERR_FOUND | INTR0_ENABLE_SET[2] ADDR_ERR_FOUND/INTR1_ENABLE_SET[2] ADDR_ERR_FOUND andINTR0_ENABLE_CLEAR[2] ADDR_ERR_FOUND/INTR1_ENABLE_CLEAR[2] ADDR_ERR_FOUND | This status flag is set when the value of the STATUS_ERROR_CNT[23:20] ADDR_ERROR_CNT bit field reaches the threshold counter value configured through the CFG_OCMC_ECC_ERROR[23:20] CFG_ADDR_ERR_CNT_MAX bit field. The status remains asserted until the counter is not cleared. This is done by setting to 0x1 the CFG_OCMC_ECC_CLEAR_HIST[2] CLEAR_ADDR_ERR_CNT bit. If the counter is not cleared another interrupt is re-issued. |
INTR0_STATUS_RAW_SET[1] DED_ERR_FOUND/INTR1_STATUS_RAW_SET[1] DED_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[1] DED_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[1] DED_ERR_FOUND | INTR0_ENABLE_SET[1] DED_ERR_FOUND/INTR1_ENABLE_SET[1] DED_ERR_FOUND andINTR0_ENABLE_CLEAR[1] DED_ERR_FOUND/INTR1_ENABLE_CLEAR[1] DED_ERR_FOUND | This status flag is set when the value of the STATUS_ERROR_CNT[19:16] DED_ERROR_CNT bit field reaches the threshold counter value configured through the CFG_OCMC_ECC_ERROR[19:16] CFG_DED_CNT_MAX bit field. The status remains asserted until the counter is not cleared. This is done by setting to 0x1 the CFG_OCMC_ECC_CLEAR_HIST[1] CLEAR_DED_ERR_CNT bit. If the counter is not cleared another interrupt is re-issued. |
INTR0_STATUS_RAW_SET[0] SEC_ERR_FOUND/INTR1_STATUS_RAW_SET[0] SEC_ERR_FOUND andINTR0_STATUS_ENABLED_CLEAR[0] SEC_ERR_FOUND/INTR1_STATUS_ENABLED_CLEAR[0] SEC_ERR_FOUND | INTR0_ENABLE_SET[0] SEC_ERR_FOUND/INTR1_ENABLE_SET[0] SEC_ERR_FOUND andINTR0_ENABLE_CLEAR[0] SEC_ERR_FOUND/INTR1_ENABLE_CLEAR[0] SEC_ERR_FOUND | This status flag is set when the value of the STATUS_ERROR_CNT[15:0] SEC_ERROR_CNT bit field reaches the threshold counter value configured through the CFG_OCMC_ECC_ERROR[15:0] CFG_SEC_CNT_MAX bit field. The status remains asserted until the counter is not cleared. This is done by setting to 0x1 the CFG_OCMC_ECC_CLEAR_HIST[0] CLEAR_SEC_ERR_CNT bit. If the counter is not cleared another interrupt is re-issued. |