SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
Figure 24-146 describes the I/O signals of the SuperSpeed USB subsystem interfaces.
i = 1 to 4
k = 3 or 4
Table 24-432 through Table 24-435 describe the I/O signals of the SuperSpeed USB subsystem interfaces shown in Figure 24-146
Module Pin | Device-Level Signal Name | I/O(1) | Description | Reset Value |
---|---|---|---|---|
USB2PHY1 | ||||
DRVVBUS | usb1_drvvbus | O | Drive-VBUS enable to external charge pump/power switch | 0 |
DP | usb1_dp | I/O | USB2.0 half-duplex differential pair | HiZ |
DM | usb1_dm | I/O | HiZ | |
USB3_PHY | ||||
TX | usb_txn0 | O | USB3.0 transmitter differential pair | HiZ |
TY | usb_txp0 | O | HiZ | |
RX | usb_rxn0 | I | USB3.0 receiver differential pair | HiZ |
RY | usb_rxp0 | I | HiZ |
Module Pin | Device-Level Signal Name | I/O | Description | Reset Value |
---|---|---|---|---|
USB2PHY2 | ||||
DRVVBUS | usb2_drvvbus | O | Drive-VBUS enable to external charge pump/power switch | 0 |
DP | usb2_dp | I/O | USB2.0 half-duplex differential pair | HiZ |
DM | usb2_dm | I/O | HiZ |
Module Pin | Device-Level Signal Name | I/O | Description | Reset Value |
---|---|---|---|---|
ULPI interface | ||||
ULPI_CLK | usb3_ulpi_clk | I | Clock input from external transceiver | HiZ |
ULPI_DIR | usb3_ulpi_dir | I | Data direction control from external transceiver | HiZ |
ULPI_STP | usb3_ulpi_stp | O | Output to external transceiver to stop data stream | 1 |
ULPI_NXT | usb3_ulpi_nxt | I | Next signal control from external transceiver | HiZ |
ULPI_DATA0 | usb3_ulpi_d0 | I/O | Data bit 0 to/from external transceiver | HiZ |
ULPI_DATA1 | usb3_ulpi_d1 | I/O | Data bit 1 to/from external transceiver | HiZ |
ULPI_DATA2 | usb3_ulpi_d2 | I/O | Data bit 2 to/from external transceiver | HiZ |
ULPI_DATA3 | usb3_ulpi_d3 | I/O | Data bit 3 to/from external transceiver | HiZ |
ULPI_DATA4 | usb3_ulpi_d4 | I/O | Data bit 4 to/from external transceiver | HiZ |
ULPI_DATA5 | usb3_ulpi_d5 | I/O | Data bit 5 to/from external transceiver | HiZ |
ULPI_DATA6 | usb3_ulpi_d6 | I/O | Data bit 6 to/from external transceiver | HiZ |
ULPI_DATA7 | usb3_ulpi_d7 | I/O | Data bit 7 to/from external transceiver | HiZ |
Module Pin | Device-Level Signal Name | I/O | Description | Reset Value |
---|---|---|---|---|
ULPI interface | ||||
ULPI_CLK | usb4_ulpi_clk | I | Clock input from external transceiver | HiZ |
ULPI_DIR | usb4_ulpi_dir | I | Data direction control from external transceiver | HiZ |
ULPI_STP | usb4_ulpi_stp | O | Output to external transceiver to stop data stream | 1 |
ULPI_NXT | usb4_ulpi_nxt | I | Next signal control from external transceiver | HiZ |
ULPI_DATA0 | usb4_ulpi_d0 | I/O | Data bit 0 to/from external transceiver | HiZ |
ULPI_DATA1 | usb4_ulpi_d1 | I/O | Data bit 1 to/from external transceiver | HiZ |
ULPI_DATA2 | usb4_ulpi_d2 | I/O | Data bit 2 to/from external transceiver | HiZ |
ULPI_DATA3 | usb4_ulpi_d3 | I/O | Data bit 3 to/from external transceiver | HiZ |
ULPI_DATA4 | usb4_ulpi_d4 | I/O | Data bit 4 to/from external transceiver | HiZ |
ULPI_DATA5 | usb4_ulpi_d5 | I/O | Data bit 5 to/from external transceiver | HiZ |
ULPI_DATA6 | usb4_ulpi_d6 | I/O | Data bit 6 to/from external transceiver | HiZ |
ULPI_DATA7 | usb4_ulpi_d7 | I/O | Data bit 7 to/from external transceiver | HiZ |
The path from a module pin to device pad(s) is defined at the device I/O logic level. The control module registers assign the specific function to the device pads. For more information on control module settings, see Pad Configuration Registers in Control Module.