The ATL module is clocked by a functional clock (ATLPCLK) and one interface clock (OCP_CLK).
- The functional clock is used to generate control
signals depending on the internal configuration of the module. The ATLPCLK
selection register mux ATL_PCLKMUX0[0] PCLKMUX chooses the functional clock for
ATLPCLK input to run error counting timers and to derive modulated ATCLK_OUT
clock outputs.
- OCP_CLK is used to trigger access to the ATL configuration interface through the L4_PER2 Interconnect.
- A software reset register is provided to hold the
four ATL modules in reset while the AWS/BWS and ATPCLK mux selections are set
and while the system-level clocking is configured. Software is required to
release the module from reset. Software must enable the ATL_SWEN0[0] SWEN bit to
enable the ATL. Each ATL in the device must be independently enabled.
Note: The module must be enabled in the PRCM. For more
information refer to PRCM Register Manual, in Power, Reset, Clock
Management Module.