SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The SRAM associated with the OCMC_RAM1 is accessible through the L3_MAIN interconnect. The start address is 0x4030 0000 and the end address is 0x4037 FFFF. That is address space of 512KiB. The configuration registers of the OCMC_RAM1 are accessible through the L4_PER3 starting at address 0x4880 4000.
The SRAM associated with the OCMC_RAM2 is accessible through the L3_MAIN interconnect. The start address is 0x4040 0000 and the end address is 0x404F FFFF. That is address space of 1MiB. The configuration registers of the OCMC_RAM2 are accessible through the L4_PER3 starting at address 0x4880 A000.
The SRAM associated with the OCMC_RAM3 is accessible through the L3_MAIN interconnect. The start address is 0x4050 0000 and the end address is 0x405F FFFF. That is address space of 1MiB. The configuration registers of the OCMC_RAM3 are accessible through the L4_PER3 starting at address 0x4881 0000.
OCMC_RAM2 and OCMC_RAM3 banks are not present on DRA74x devices, but are included in some of the DRA75x devices. For details, see the device data manual.