SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
This mode is used if the TSICR[2] POSTED bit is set to 1.
This mode uses a posted write scheme to update any internal register (TCLR, TCRR, TLDR, TTGR, TMAR, and TPIR, TNIR, TCVR, TOCR, and TOWR for TIMER1, TIMER2, and TIMER10). Therefore, the write transaction is immediately acknowledged on the open-core protocol (OCP) interface, although the effective write operation occurs later because of a resynchronization in the timer clock domain. The advantage is that neither the interconnect nor the device that requested the write transaction is stalled.
For each register, a status bit is provided in the timer write-posted status (TWPS) register. In this mode, it is mandatory that software check this status bit before any write access. If a write is attempted to a register with a previous access pending, the previous access is discarded without notice.
The timer module updates the value of the timer counter register synchronously with the OCP clock. Consequently, any read access to TCRR does not add any resynchronization latency; the current value is always available.
Because the overflow IRQ is generated when the value of TCRR reaches 0xFFFF FFFF, and not when it changes its value to the value after overflow, it is necessary to wait a delay of (1 × PS × timer functional clock period) before any read access to TCRR to ensure a correct reading of its content.
If TTGR register is written during posted write to TCRR, the value to be written to TCRR will be discarded.
If a posted write to TCVR is started, the user must not write to TPIR or TNIR before the TCVR write is finished, because the value of TCVR is re-evaluated, so both the value to be written, and the recalculated value will be discarded.
If a write access is pending for a register, reading from this register does not yield a correct result. Software synchronization must be used to avoid incorrect results.
Functional frequency range: freq(timer clock) < freq(OCP interface clock) / 4.