SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
As the complexity of SoC architectures increases, system and subsystem optimization requires increased visibility into the frequency and duration of events within the system. One way to address these profiling requirements is to embed dedicated event or profile counters in all functional modules with profiling requirements. While this can address the fundamental requirements, there are several disadvantages to this approach:
This section defines the functional specification for a generic counter timer module that can be instantiated within the processor subsystem and that also functions as a centralized profiling module for the entire subsystem. This module maps a large number of system and subsystem event signals to a smaller number of counter resources. Some of the counter resources in the module can be configured for timer functionality where system and/or debug events can be generated when designated intervals are matched.
In the EVE subsystem eight 32-bit counters are instantiated. Two of those eight counters can be configured as timers.
The generic centralized counter timer approach provides several advantages: