SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The MPU subsystem power domain (PD_MPU) must be at a higher or equal power state (a state that consumes more power) than the higher of the two MPU cores. For example, it is illegal for the MPU subsystem power state to be RETENTION, while the power state of one or both of the MPU cores is ON.
Software must ensure that only legal power states are programmed. When an illegal state is entered, the behavior of the hardware is unpredictable.
Table 4-8 lists the MPU subsystem legal power states.
Hardware Conditions | MPU/System Programming Model | Resulting MPU/System State | |||||||
---|---|---|---|---|---|---|---|---|---|
MPU_Cx States | State of L2 | PRCM Power State PM_MPU_PWRSTCTRL[1:0] POWERSTATE | PRCM Logic Retention State PM_MPU_PWRSTCTRL[2] LOGICRETSTATE | PRCM L2 Memory Retention State PM_MPU_PWRSTCTRL[9] MPU_L2_RETSTATE | PRCM Clock Transition Control CM_MPU_CLKSTCTRL[1:0] CLKTRCTRL | Logic | L2 Cache | DPLL Clock | Power State (at PRCM) |
At least one is ON | Any | Any | Any | Any | Any | ON | ON | ON | ON |
Any | != (IDLE / WFI) | Any | Any | Any | Any | ON | ON | ON | ON |
Power state of both MPU cores is less than or equal to INACT | IDLE / WFI | Any | Any | Any | NO_SLEEP/SW_WKUP | ON | ON | ON | ON |
IDLE / WFI | ON | Any | Any | HW_AUTO | ON | ON | ON | ON | |
IDLE / WFI | INACT | Any | Any | HW_AUTO | ON | ON | OFF | INACT | |
Power state of both MPU cores is less than or equal to CSWRET | IDLE / WFI | RETENTION | CSWRET | RETENTION | HW_AUTO | ON | RETENTION | OFF | CSWRET |
IDLE / WFI | RETENTION | CSWRET | OFF | HW_AUTO | ON | OFF | OFF | CSWRET |
All the transitions presented in Table 4-8, except for the first line, are handled by the MPU_PRCM and the global PRCM.
Once the MPU subsystem reaches a low-power state (INACT, CSWRET), it cannot move to another low-power state. It must be woken up to reach another low-power state.