There is no direct software gate control for the DPLL_PCIE_REF.CLKOUTLDO output.
DPLL_PCIE_REF.CLKOUTLDO clock output is automatically gated (CLKOUTLDO pulled low) in the following scenarios:
- DPLL power-up sequence. For more information on power-up sequence, see Section 26.4.4.4.1.6.1, PCIe PHY Clock Generator Power Up.
- DPLL entering a relock sequence. For more information on relocking sequence, see Section 26.4.4.4.1.6.2, PCIe PHY DPLL Sequences.
- DPLL entering Idle-bypass low-power mode. For more information on idle-bypass mode, see Section 26.4.4.4.1.6.4, PCIe PHY DPLL Idle-Bypass Mode.
- DPLL entering Low Power Stop mode. For more information on Low Power Stop mode, see Section 26.4.4.4.1.6.5, PCIe PHY DPLL Low Power Stop Mode.