SPRUI30H November 2015 – May 2024 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
The GPMC generates one interrupt request (see Figure 15-57).
Table 15-422 lists the event flags, and their mask, that can cause module interrupts.
Event Flag | Event Mask | Sensitivity | Description |
---|---|---|---|
GPMC_IRQSTATUS[9] WAIT1EDGE DETECTIONSTATUS | GPMC_IRQENABLE[9] WAIT1EDGE DETECTIONENABLE | Edge | Wait1 edge detection interrupt: Triggered if a rising or falling edge is detected on the gpmc_wait1 signal. The rising or falling edge detection of Wait1 is selected through the GPMC_CONFIG[9] WAIT1PINPOLARITY bit. |
GPMC_IRQSTATUS[8] WAIT0EDGE DETECTIONSTATUS | GPMC_IRQENABLE[8] WAIT0EDGE DETECTIONENABLE | Edge | Wait0 edge detection interrupt: Triggered if a rising or falling edge is detected on the gpmc_wait0 signal. The rising or falling edge detection of Wait0 is selected through the GPMC_CONFIG[8] WAIT0PINPOLARITY bit. |
GPMC_IRQSTATUS[1] TERMINAL COUNTSTATUS | GPMC_IRQENABLE[1] TERMINAL COUNTENABLE | Level | Terminal count event: Triggered on prefetch process completion; that is, when the number of currently remaining data to be requested reaches 0 |
GPMC_IRQSTATUS[0] FIFOEVENTSTATUS | GPMC_IRQENABLE[0] FIFOEVENTENABLE | Level | FIFO event interrupt: Indicates available FIFO levels for write-posting mode and prefetch mode. GPMC_PREFETCH_CONFIG1[2] DMAMODE must be set to 0. |