SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The L3 (master) interconnect generates data traffic within the device. The L4 (slave) interconnect is a configuration port for register setting.
Figure 24-150 shows the SuperSpeed USB subsystem integration in the device.
i = 1 to 4
k = 3 or 4
Table 24-436 through Table 24-438 summarize the integration of the module in the device.
Module Instance | Attributes | |
Power Domain | Interconnect | |
USB1 | PD_L3INIT | L3_MAIN L4_PER3 |
USB2 | PD_L3INIT | L3_MAIN L4_PER3 |
USB3 | PD_L3INIT | L3_MAIN L4_PER3 |
USB4 | PD_L3INIT | L3_MAIN L4_PER3 |
USB2PHY1 | PD_L3INIT | L4_CFG |
USB2PHY2 | PD_L3INIT | L4_CFG |
USB3_PHY | PD_L3INIT | L4_CFG |
Table 24-437 lists the clocks provided to the SuperSpeed USB subsystem.
Clocks | ||||
Module Instance | Destination Signal Name | Source Signal Name | Source | Description |
USB1 | USB1_FCLK | USB2PHY1_UTMI_CLK | USB2PHY1 | 60-MHz UTMI clock from PHY |
USB1_MICLK | L3INIT_L3_GICLK | PRCM | L3 interconnect clock, for the L3 master port interface CD_L3INIT Clock Domain in Power, Reset and Clock Management. | |
USB1_SUSP_CLK | USB_OTG_SS_REF_CLK | PRCM | Suspend clock | |
USB2 | USB2_FCLK | USB2PHY2_UTMI_CLK | USB2PHY2 | 60-MHz UTMI clock from PHY |
USB2_MICLK | L3INIT_L3_GICLK | PRCM | L3 interconnect clock, for the L3 master port interface. | |
USB2_SUSP_CLK | USB_OTG_SS_REF_CLK | PRCM | Suspend clock | |
USB2_125M_CLK | L3INIT_60M_FCLK | PRCM | 125-MHz clock for the non-USB3.0 instances. | |
USB3 | USB3_FCLK | OTG_60M_FCLK | usb3_ulpi_clk pad | 60-MHz ULPI clock from PHY |
USB3_MICLK | L3INIT_L3_GICLK | PRCM | L3 interconnect clock, for the L3 master port interface . | |
USB3_SUSP_CLK | USB_OTG_SS_REF_CLK | PRCM | Suspend clock | |
USB3_125M_CLK | L3INIT_60M_FCLK | PRCM | 125-MHz clock for the non-USB3.0 instances. | |
USB4 | USB4_FCLK | OTG_60M_FCLK | usb4_ulpi_clk pad | 60-MHz ULPI clock from PHY |
USB4_MICLK | L3INIT_L3_GICLK | PRCM | L3 interconnect clock, for the L3 master port interface . | |
USB4_SUSP_CLK | USB_OTG_SS_REF_CLK | PRCM | Suspend clock | |
USB4_125M_CLK | L3INIT_60M_FCLK | PRCM | 125-MHz clock for the non-USB3.0 instances. | |
USB2PHY1 | USB2PHY1_REF_CLK | L3INIT_960M_GFCLK | PRCM | Functional REF 960-MHz clock (from the DPLL_USB, PRCM controlled) |
USB2PHY1_WKUP_CLK | FUNC_32K_CLK | PRCM | Wakeup 32-kHz functional clock | |
USB2PHY1_TREF_CLK | USB_OTG_SS_REF_CLK | PRCM | Functional TREF clock derived from SYS_CLK1 | |
USB2PHY2 | USB2PHY2_REF_CLK | L3INIT_960M_GFCLK | PRCM | Functional REF 960-MHz clock (from the DPLL_USB, PRCM controlled) |
USB2PHY2_WKUP_CLK | FUNC_32K_CLK | PRCM | Wakeup 32-kHz functional clock | |
USB2PHY2_TREF_CLK | USB_OTG_SS_REF_CLK | PRCM | Functional TREF clock derived from SYS_CLK1 | |
USB3_PHY | USB3PHY_REF_CLK | USB_LFPS_TX_GFCLK | PRCM | Fixed-frequency USB3 transmitter REF functional clock |
DPLL_USBSS_REF_CLK | USB_OTG_SS_REF_CLK | PRCM | Functional DPLL REF clock derived from SYS_CLK1 | |
USB3PHY_WKUP_CLK | COREAON_32K_GFCLK | PRCM | Wakeup and debounce 32-kHz functional clock | |
Resets | ||||
Module Instance | Destination Signal Name | Source Signal Name | Source | Description |
USB1 | USB1_RST | L3INIT_RET_RST | PRCM | USB1 controller module hardware retention reset |
USB2 | USB2_RST | L3INIT_RET_RST | PRCM | USB2 controller module hardware retention reset |
USB3 | USB3_RST | L3INIT_RET_RST | PRCM | USB3 controller module hardware retention reset |
USB4 | USB4_RST | L3INIT_RET_RST | PRCM | USB4 controller module hardware retention reset |
Table 24-438 lists the interrupt lines that are driven out from the SuperSpeed USB controller modules.
Interrupt Requests | ||||
Module Instance | Source Signal Name | IRQ_CROSSBAR Input | Default Mapping | Description |
USB1 | USB1_IRQ_INTR0 | IRQ_CROSSBAR_71 | MPU_IRQ_76 | USB1 main (core) interrupt request |
USB1_IRQ_INTR1 | IRQ_CROSSBAR_72 | MPU_IRQ_77 IPU1_IRQ_73 IPU2_IRQ_73 | USB1 wrapper interrupt request | |
USB2 | USB2_IRQ_INTR0 | IRQ_CROSSBAR_73 | MPU_IRQ_78 IPU1_IRQ_74 IPU2_IRQ_74 | USB2 main (core) interrupt request |
USB2_IRQ_INTR1 | IRQ_CROSSBAR_87 | MPU_IRQ_92 IPU1_IRQ_76 IPU2_IRQ_76 | USB2 wrapper interrupt request | |
USB3 | USB3_IRQ_INTR0 | IRQ_CROSSBAR_88 | MPU_IRQ_93 IPU1_IRQ_77 IPU2_IRQ_77 | USB3 main (core) interrupt request |
USB3_IRQ_INTR1 | IRQ_CROSSBAR_344 | - | USB3 wrapper interrupt request | |
USB4 | USB4_IRQ_INTR0 | IRQ_CROSSBAR_345 | - | USB4 main (core) interrupt request |
USB4_IRQ_INTR1 | IRQ_CROSSBAR_346 | - | USB4 wrapper interrupt request |
The Default Mapping column in Table 24-438 shows the default mapping of module IRQ source signals. These IRQ source signals can also be mapped to other lines of each device Interrupt controller through the IRQ_CROSSBAR module. For more information about the IRQ_CROSSBAR module, see IRQ_CROSSBAR Module Functional Description, in Control Module.
For more information about the device interrupt controllers, see Interrupt Controllers.