SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
This section describes how the overall PCI express functionality is implemented by the current controller, both as EP and as RC, and how each type of traffic is transmitted and received.
The PCI express interface allows memory-mapped read and write transactions to be performed across different partners of the same PCIe fabric. Locally the device local PCIe system is composed of the PCIe_SS controller itself, device local hosts (such as MPU, DSP, and so forth), device DMAs (EDMA, and so forth) and device system memory (EMIFs SDRAM), connected to the PCIe controller via L3_MAIN interconnect.
Figure 24-161 summarizes the functional components of the PCIe_SS controller, as well as the connectivity between PCIe_SS and other components (MMU2, IRQ_CROSBBAR, PRCM, and so forth) within the device.