SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
As part of the system-wide power-management scheme, the L3_MAIN interconnect goes into IDLE state after receiving a request from the power, reset, and clock management (PRCM) module after all commands are serviced. This function is handled by hardware.
To reduce power consumption, the L3_MAIN interconnect automatically performs internal clock autogating. This is managed by hardware; no software configurations or settings are required.
L3_MAIN supports a partial retention scheme. Retention is performed on the follwoing registers:
This process prevents reconfiguration after a clock domain switches off.