SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
In FIFO polling mode (the I2Ci.I2C_IRQENABLE_SET [4] XRDY_IE and I2Ci.I2C_IRQENABLE_SET [3] RRDY_IE bits are disabled), the status of the module (receiver or transmitter) can be checked by polling the I2Ci.I2C_IRQSTATUS_RAW [4] XRDY and the I2Ci.I2C_IRQSTATUS_RAW [3] RRDY bits (the I2Ci.I2C_IRQSTATUS_RAW [13] RDR and I2Ci.I2C_IRQSTATUS_RAW [14] XDR bits can also be polled if the draining feature is enabled). The I2Ci.I2C_IRQSTATUS_RAW [4] XRDY and I2Ci.I2C_IRQSTATUS_RAW [3] RRDY bits accurately reflect the interrupt conditions described in the discussion of FIFO interrupt mode.