SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
Table 9-29 shows how the scaler should be configured based on the scale factor and the input/output mode.
Interlace | Mode(1) | VIP_CFG_SC5[10:0] CFG_SRC_H mod_srcH | VIP_CFG_SC4[10:0] CFG_TAR_H mod_tarH | Scale Factor | ||
In | Out | |||||
0 | 0 | p->p | CFG_SRC_H | CFG_TAR_H | CFG_TAR_H/CFG_SRC_H | |
0 | 1 | p->i | CFG_SRC_H | CFG_TAR_H/2 | CFG_TAR_H/CFG_SRC_H | |
1 | 0 | i->p | CFG_SRC_H/2 | CFG_TAR_H | CFG_TAR_H/(CFG_SRC_H/2) | |
1 | 1 | i->i | CFG_SRC_H/2 | CFG_TAR_H/2 | (CFG_TAR_H/2)/(CFG_SRC_H/2) |
Table 9-30 shows how the vertical scaler should be configured based on the scale factor and the input/output mode.
Interlace | Mode(1) | VIP_CFG_SC9[26:24] CFG_ROW_ACC_INC/216 | VIP_CFG_SC6[9:0] CFG_ROW_ACC_INIT_RAV/216 | VIP_CFG_SC6[19:10] CFG_ROW_ACC_INIT_RAV_B/216 | |
In | Out | Top | Bot | ||
0 | 0 | p->p | (CFG_SRC_H-1)/(CFG_TAR_H-1) | 0 | 0 |
0 | 1 | p->i | 2*(CFG_SRC_H-1)/(CFG_TAR_H-1) | 0 | (CFG_SRC_H-1)/(CFG_TAR_H-1) |
1 | 0 | i->p | 1/2*(CFG_SRC_H-1)/(CFG_TAR_H-1) | 0 | -0.5 |
1 | 1 | i->i | (CFG_SRC_H-1)/(CFG_TAR_H-1) | 0 | [(CFG_SRC_H-1)/(CFG_TAR_H-1)-1]/2 |