SPRUI30H November 2015 – May 2024 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
The McASP receive clock generator is built on a very similar to the transmit clock generator (but independent) circuit.
The receive clock configuration is controlled by the following registers:
In case, the receive bit clock, ACLKR, is generated internally (but asynchronously to XCLK), the MCASP_ACLKRCTL[5] CLKRM bit must be set to 1. Thus, the clock is divided down by a programmable bit clock divider (the MCASP_ACLKRCTL[4:0] CLKRDIV bit field) from the source signal.
If the receive high-frequency master clock, AHCLKR, is also sourced internally (that is, first scenario described in Section 24.6.4.2) and the MCASP_AHCLKRCTL[15] HCLKRM bit must be set to 1. Thus, the clock is divided down by a programmable high-clock divider (the MCASP_AHCLKRCTL[11:0] HCLKRDIV bit field) from the McASP internal clock source AUXCLK.
The polarity of ACLKR can be controlled in MCASP_ACLKRCTL[7] CLKRP, regardless of ACLKR signal being internally or externally sourced.
In a similar way, the polarity of AHCLKR clock can be controlled in MCASP_AHCLKRCTL[14] HCLKRP, regardless of the AHCLKR signal being internally or externally sourced.
There is an option for the McASP receiver to be configured to operate synchronously to the ACLKX and AFSX signals. The XCLK output of the Tx Clock generator (see Figure 24-120 and Figure 24-121) becomes source of the receive clock (RCLK output), when the MCASP_ACLKXCTL[6] ASYNC bit in the transmit clock control register is set to '0b0'. For more information, refer to Section 24.6.4.2.4.
Figure 24-121 is the block diagram of the receive clock generator.
In this device:
For more on McASP integration, see Section 24.6.2, McASP Environment, and Section 24.6.3, McASP Integration.