SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The PCIe PHY component receives a feedback clock, PIPE_MCLK, which is the loopback version of the PIPE_PCLK (PIPE port synchronizing clock) generated by the PCIe PHY component. The clock is turned on/off according to the PIPE power-down port states. As PIPE port works in source-synchronous mode, all data movement from the MAC layer to the PIPE interface is synchronous to PIPE_PCLK.
The high speed transmission clock input of the PCIe_PHY serializer and deserializer are connected to APLL_PCIE output pins. The PHY_RX module input clock pin is tied to APLL_PCIE_REF.CLKVCOLDO (PCIE_PHY_GCLK) clock. The PHY_TX input clock pin is tied to divided APLL_PCIE_REF.CLKVCOLDO_DIV (PCIE_PHY_DIV_GCLK) output clock. For more information on the APLL_PCIE_REF.CLKVCOLDO and APLL_PCIE_REF.CLKVCOLDO_DIV output clocks settings, see Section 26.4.4.4.1.4.2, PCIe PHY APLL Output Clock Configuration.
In two lane mode when both PCIe1_PHY and PCIe2_PHY modules are connected to PCIe_SS1 as Lane-0 and Lane-1, there is a requirement for the clocking of the transmitter parts PCIe1_PHY_TX and PCIe2_PHY_TX. Both input clocks of the transmitters of all ports has to be in phase, including the by-2-dividers used when operating in 2.5GT/s. This is implemented by providing the same pre-divided clock to the PCIe1_PHY_TX and PCIe2_PHY_TX, coming from the APLL_PCIE’s own by-2-divider, and bypassing the by-2-dividers inside each PCIe1_PHY_TX and PCIe2_PHY_TX. In this way the PCIe1_PHY_TX and PCIe2_PHY_TX receive one high speed clock and are allways in phase. The receivers PCIe1_PHY_RX and PCIe2_PHY_RX do not need synchronization in two lane mode.
The high speed clock APLL_PCIE_REF.CLKVCOLDO_DIV (PCIE_PHY_DIV_GCLK) could be divided by 2 on two places, in the APLL_PCIE own by-2-divider or in the PHY_TX internal by-2-divider. These dividers support force-bypass mode where the divider is bypassed and no division is performed. The dividers of the APLL_PCIE and of the PHY_TX are cascaded: one divider should always be bypassed, and the other active. For one lane operation the APLL_PCIE divider could be force-baypassed and only internal PCIe_PHY divider to be active.
The APLL_PCIE by-2-divider bypass is controlled in PRCM register CM_CLKMODE_APLL_PCIE[8] CLKDIV_BYPASS bit.
The PCIe1_PHY_TX by-2-divider bypass mode is controlled by PCIe1_PHY_TX.PCIEPHYTX_DRIVER_DATA_CONFIG1 register bits as follows:
PCIEPHYTX_DRIVER_DATA_CONFIG1[1] MEM_OVRD_HS_RATE_ANA_OVERRIDE = 0b0
PCIEPHYTX_DRIVER_DATA_CONFIG1[1] MEM_OVRD_HS_RATE_ANA_OVERRIDE = 0b1
PCIEPHYTX_DRIVER_DATA_CONFIG1[3:2] MEM_HS_RATE_ANA_OVERRIDE = 0b00
The receivers PCIe1_PHY_RX and PCIe2_PHY_RX are allways supplied with non divided clock APLL_PCIE_REF.CLKVCOLDO (PCIE_PHY_GCLK) and the internal dividersare always active and controlled by the PCIe controllers.
The APLL_PCIE input clock is MUX selectable between DPLL_PCIE_REF.CLKOUTLDO output and ACSPCIE output derived from device differential clock input pins.
The DPLL_PCIE_REF input clock pin CLKINP is tied to PRCM.PCIE_DPLL_CLK (SYS_CLK1 based) clock.
As shown in Table 26-51, the PCIe PHY Power control module clock input is supplied from SYS_CLK1 based clock PRCM.PCIE_SYS_GFCLK.
Software must notify the PHY logic about which clock frequency is selected by writing CTRL_CORE_PHY_POWER_PCIESS1[31:22] PCIESS1_PWRCTL_CLKFREQ bit field and CTRL_CORE_PHY_POWER_PCIESS2[31:22] PCIESS2_PWRCTL_CLKFREQ bit field.
The REF_CLKIN clock input is used to support different PCIe_PHY functions. REF_CLKIN clock input is tied to the PRCM.PCIE_REF_GFCLK (CORE_USB_OTG_SS_LFPS_TX_CLK based) functional clock.
The PCIE1_PHY_RX deserializer I/O wake-up logic is supported by the PRCM.PCIE_32K_GFCLK clock, applied at the logic clock input.
The input clock for PCIe_PHY SCP port configuration interface is delivered from the OCP2SCP3 interface adaclockpter.
The SCP port clock input of PCIe_PHY is driven by the OCP2SCP3 gateable output . The ratio of the OCP2SCP3 gateable output clock to the OCP2SCP3 input clock (L3INIT_L4_GICLK) is controlled through the OCP2SCP_TIMING[9:7] DIVISIONRATIO bit field. For more information, see Section 26.4.4.2.3, OCP2SCP3 Timing Registers.