The address sent out to data memory is always a word address. Access sizes smaller than word size are supported via byte enables.
The CPU core asserts the memory request signal (active low, cpu_dmem_enz_o) along with corresponding address (cpu_dmem_addr_o) and read/write qualifier (active low, cpu_dmem_wrz_o) until a ready (active high, cpu_dmem_rdy_i) is received from the memory sub-system.
For a zero-wait state access, the ready is expected next cycle to the request. Ready must be de-asserted to extend the access cycle for a higher wait state memory subsystem.
For read accesses, the CPU samples the read data bus (cpu_dmem_rdata_i[31:0]) when ready is asserted. For write accesses, ready indicates write completion whereas read data bus is a don’t care.
For writes accesses, appropriate byte enables (active low, cpu_dmem_bez[3:0]) are asserted in request phase. This is the only way for the memory sub-system to identify access size of a write access. Byte steering is done by the core, hence the memory sub-system can use the ANY lanes of write data bus for easy selections/multiplexing of write data - for byte writes, the write data is duplicated on all four byte lanes of write data bus whereas for halfword writes, the write data is duplicated on both the halfword lanes of write data bus.
For read accesses, access size is always 32b - the memory sub-system always returns 32b at the requested word address. CPU core selects the appropriate bytes based on access size and access address.