SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 3-378 lists the memory-mapped registers for the DCSM_BANK0_Z1_OTP registers. All register offset addresses not listed in Table 3-378 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | B0_Z1OTP_LINKPOINTER1 | Zone 1 Link Pointer1 in Z1 OTP for flash BANK0 | Go | |
4h | B0_Z1OTP_LINKPOINTER2 | Zone 1 Link Pointer2 in Z1 OTP for flash BANK0 | Go | |
8h | B0_Z1OTP_LINKPOINTER3 | Zone 1 Link Pointer3 in Z1 OTP for flash BANK0 | Go | |
Ch | Z1OTP_BOOTPIN_CONFIG | Boot Pin Configuration | Go | |
Eh | Z1OTP_GPREG2 | Zone-1 General Purpose Register-2 content | Go | |
10h | Z1OTP_PSWDLOCK | Secure Password Lock in Z1 OTP | Go | |
14h | Z1OTP_CRCLOCK | Secure CRC Lock in Z1 OTP | Go | |
18h | Z1OTP_JTAGLOCK | Secure JTAG Lock in Z1 OTP | Go | |
1Ch | Z1OTP_BOOTDEF_LOW | Boot definition (low 32bit) | Go | |
1Eh | Z1OTP_BOOTDEF_HIGH | Boot definition (high 32bit) | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-379 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
B0_Z1OTP_LINKPOINTER1 is shown in Figure 3-338 and described in Table 3-380.
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Zone 1 Link Pointer1 in Z1 OTP for flash BANK0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
B0_Z1OTP_LINKPOINTER1 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | B0_Z1OTP_LINKPOINTER1 | R | FFFFFFFFh | Zone1 Link Pointer 1 location in USER OTP of Flash BANK0. Reset type: SYSRSn |
B0_Z1OTP_LINKPOINTER2 is shown in Figure 3-339 and described in Table 3-381.
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Zone 1 Link Pointer2 in Z1 OTP for flash BANK0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
B0_Z1OTP_LINKPOINTER2 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | B0_Z1OTP_LINKPOINTER2 | R | FFFFFFFFh | Zone1 Link Pointer 2 location in USER OTP of Flash BANK0. Reset type: SYSRSn |
B0_Z1OTP_LINKPOINTER3 is shown in Figure 3-340 and described in Table 3-382.
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Zone 1 Link Pointer3 in Z1 OTP for flash BANK0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
B0_Z1OTP_LINKPOINTER3 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | B0_Z1OTP_LINKPOINTER3 | R | FFFFFFFFh | Zone1 Link Pointer 3 location in USER OTP of Flash BANK0. Reset type: SYSRSn |
Z1OTP_BOOTPIN_CONFIG is shown in Figure 3-341 and described in Table 3-383.
Return to the Summary Table.
Boot Pin Configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_BOOTPIN_CONFIG | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_BOOTPIN_CONFIG | R | FFFFFFFFh | Zone1 Boot pin configuration register location in USER OTP of Flash BANK0. Reset type: SYSRSn |
Z1OTP_GPREG2 is shown in Figure 3-342 and described in Table 3-384.
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Zone-1 General Purpose Register-2 content
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_GPREG2 | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_GPREG2 | R | FFFFFFFFh | Zone1 General Purpose register location in USER OTP of Flash BANK0. Reset type: SYSRSn |
Z1OTP_PSWDLOCK is shown in Figure 3-343 and described in Table 3-385.
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Secure Password Lock in Z1 OTP
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_PSWDLOCK | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_PSWDLOCK | R | FFFFFFFFh | Zone1 password lock location in USER OTP of Flash BANK0. Reset type: SYSRSn |
Z1OTP_CRCLOCK is shown in Figure 3-344 and described in Table 3-386.
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Secure CRC Lock in Z1 OTP
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_CRCLOCK | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_CRCLOCK | R | FFFFFFFFh | Zone1 CRC lock location in USER OTP of Flash BANK0. Reset type: SYSRSn |
Z1OTP_JTAGLOCK is shown in Figure 3-345 and described in Table 3-387.
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Secure JTAG Lock in Z1 OTP
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | FFFFFFFFh | Reserved |
Z1OTP_BOOTDEF_LOW is shown in Figure 3-346 and described in Table 3-388.
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Boot definition (low 32bit)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_BOOTDEF_LOW | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_BOOTDEF_LOW | R | FFFFFFFFh | Zone1 Boot definition (low) register location in USER OTP of Flash BANK0. Reset type: SYSRSn |
Z1OTP_BOOTDEF_HIGH is shown in Figure 3-347 and described in Table 3-389.
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Boot definition (high 32bit)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Z1OTP_BOOTDEF_HIGH | |||||||||||||||||||||||||||||||
R-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | Z1OTP_BOOTDEF_HIGH | R | FFFFFFFFh | Zone1 Boot Definition (high)register location in USER OTP of Flash BANK0. Reset type: SYSRSn |