SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 9-25 lists the memory-mapped registers for the XBAR_REGS registers. All register offset addresses not listed in Table 9-25 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | XBARFLG1 | X-Bar Input Flag Register 1 | Go | |
2h | XBARFLG2 | X-Bar Input Flag Register 2 | Go | |
4h | XBARFLG3 | X-Bar Input Flag Register 3 | Go | |
6h | XBARFLG4 | X-Bar Input Flag Register 4 | Go | |
8h | XBARCLR1 | X-Bar Input Flag Clear Register 1 | Go | |
Ah | XBARCLR2 | X-Bar Input Flag Clear Register 2 | Go | |
Ch | XBARCLR3 | X-Bar Input Flag Clear Register 3 | Go | |
Eh | XBARCLR4 | X-Bar Input Flag Clear Register 4 | Go |
Complex bit access types are encoded to fit into small table cells. Table 9-26 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
XBARFLG1 is shown in Figure 9-24 and described in Table 9-27.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CMPSS8_CTRIPOUTH | CMPSS8_CTRIPOUTL | CMPSS7_CTRIPOUTH | CMPSS7_CTRIPOUTL | CMPSS6_CTRIPOUTH | CMPSS6_CTRIPOUTL | CMPSS5_CTRIPOUTH | CMPSS5_CTRIPOUTL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPSS4_CTRIPOUTH | CMPSS4_CTRIPOUTL | CMPSS3_CTRIPOUTH | CMPSS3_CTRIPOUTL | CMPSS2_CTRIPOUTH | CMPSS2_CTRIPOUTL | CMPSS1_CTRIPOUTH | CMPSS1_CTRIPOUTL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CMPSS8_CTRIPH | CMPSS8_CTRIPL | CMPSS7_CTRIPH | CMPSS7_CTRIPL | CMPSS6_CTRIPH | CMPSS6_CTRIPL | CMPSS5_CTRIPH | CMPSS5_CTRIPL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPSS4_CTRIPH | CMPSS4_CTRIPL | CMPSS3_CTRIPH | CMPSS3_CTRIPL | CMPSS2_CTRIPH | CMPSS2_CTRIPL | CMPSS1_CTRIPH | CMPSS1_CTRIPL |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CMPSS8_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS8_CTRIPOUTH input was triggered 0: CMPSS8_CTRIPOUTH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
30 | CMPSS8_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS8_CTRIPOUTL input was triggered 0: CMPSS8_CTRIPOUTL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
29 | CMPSS7_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS7_CTRIPOUTH input was triggered 0: CMPSS7_CTRIPOUTH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
28 | CMPSS7_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS7_CTRIPOUTL input was triggered 0: CMPSS7_CTRIPOUTL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
27 | CMPSS6_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS6_CTRIPOUTH input was triggered 0: CMPSS6_CTRIPOUTH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
26 | CMPSS6_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS6_CTRIPOUTL input was triggered 0: CMPSS6_CTRIPOUTL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
25 | CMPSS5_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS5_CTRIPOUTH input was triggered 0: CMPSS5_CTRIPOUTH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
24 | CMPSS5_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS5_CTRIPOUTL input was triggered 0: CMPSS5_CTRIPOUTL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
23 | CMPSS4_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS4_CTRIPOUTH input was triggered 0: CMPSS4_CTRIPOUTH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
22 | CMPSS4_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS4_CTRIPOUTL input was triggered 0: CMPSS4_CTRIPOUTL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
21 | CMPSS3_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS3_CTRIPOUTH input was triggered 0: CMPSS3_CTRIPOUTH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
20 | CMPSS3_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS3_CTRIPOUTL input was triggered 0: CMPSS3_CTRIPOUTL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
19 | CMPSS2_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS2_CTRIPOUTH input was triggered 0: CMPSS2_CTRIPOUTH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
18 | CMPSS2_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS2_CTRIPOUTL input was triggered 0: CMPSS2_CTRIPOUTL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
17 | CMPSS1_CTRIPOUTH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS1_CTRIPOUTH input was triggered 0: CMPSS1_CTRIPOUTH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
16 | CMPSS1_CTRIPOUTL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS1_CTRIPOUTL input was triggered 0: CMPSS1_CTRIPOUTL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
15 | CMPSS8_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS8_CTRIPH input was triggered 0: CMPSS8_CTRIPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
14 | CMPSS8_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS8_CTRIPL input was triggered 0: CMPSS8_CTRIPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
13 | CMPSS7_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS7_CTRIPH input was triggered 0: CMPSS7_CTRIPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
12 | CMPSS7_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS7_CTRIPL input was triggered 0: CMPSS7_CTRIPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
11 | CMPSS6_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS6_CTRIPH input was triggered 0: CMPSS6_CTRIPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
10 | CMPSS6_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS6_CTRIPL input was triggered 0: CMPSS6_CTRIPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
9 | CMPSS5_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS5_CTRIPH input was triggered 0: CMPSS5_CTRIPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
8 | CMPSS5_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS5_CTRIPL input was triggered 0: CMPSS5_CTRIPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
7 | CMPSS4_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS4_CTRIPH input was triggered 0: CMPSS4_CTRIPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
6 | CMPSS4_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS4_CTRIPL input was triggered 0: CMPSS4_CTRIPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
5 | CMPSS3_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS3_CTRIPH input was triggered 0: CMPSS3_CTRIPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
4 | CMPSS3_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS3_CTRIPL input was triggered 0: CMPSS3_CTRIPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
3 | CMPSS2_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS2_CTRIPH input was triggered 0: CMPSS2_CTRIPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
2 | CMPSS2_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS2_CTRIPL input was triggered 0: CMPSS2_CTRIPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
1 | CMPSS1_CTRIPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS1_CTRIPH input was triggered 0: CMPSS1_CTRIPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
0 | CMPSS1_CTRIPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CMPSS1_CTRIPL input was triggered 0: CMPSS1_CTRIPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
XBARFLG2 is shown in Figure 9-25 and described in Table 9-28.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ADCCEVT1 | ADCBEVT4 | ADCBEVT3 | ADCBEVT2 | ADCBEVT1 | ADCAEVT4 | ADCAEVT3 | ADCAEVT2 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADCAEVT1 | EXTSYNCOUT | ECAP6_OUT | ECAP5_OUT | ECAP4_OUT | ECAP3_OUT | ECAP2_OUT | ECAP1_OUT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INPUT14 | INPUT13 | INPUT12 | INPUT11 | INPUT10 | INPUT9 | INPUT8 | INPUT7 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCSOCB | ADCSOCA | INPUT6 | INPUT5 | INPUT4 | INPUT3 | INPUT2 | INPUT1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ADCCEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCCEVT1 input was triggered 0: ADCCEVT1 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
30 | ADCBEVT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCBEVT4 input was triggered 0: ADCBEVT4 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
29 | ADCBEVT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCBEVT3 input was triggered 0: ADCBEVT3 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
28 | ADCBEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCBEVT2 input was triggered 0: ADCBEVT2 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
27 | ADCBEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCBEVT1 input was triggered 0: ADCBEVT1 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
26 | ADCAEVT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCAEVT4 input was triggered 0: ADCAEVT4 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
25 | ADCAEVT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCAEVT3 input was triggered 0: ADCAEVT3 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
24 | ADCAEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCAEVT2 input was triggered 0: ADCAEVT2 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
23 | ADCAEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCAEVT1 input was triggered 0: ADCAEVT1 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
22 | EXTSYNCOUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: EXTSYNCOUT input was triggered 0: EXTSYNCOUT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
21 | ECAP6_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ECAP6_OUT input was triggered 0: ECAP6_OUT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
20 | ECAP5_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ECAP5_OUT input was triggered 0: ECAP5_OUT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
19 | ECAP4_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ECAP4_OUT input was triggered 0: ECAP4_OUT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
18 | ECAP3_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ECAP3_OUT input was triggered 0: ECAP3_OUT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
17 | ECAP2_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ECAP2_OUT input was triggered 0: ECAP2_OUT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
16 | ECAP1_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ECAP1_OUT input was triggered 0: ECAP1_OUT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
15 | INPUT14 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT14 input was triggered 0: INPUT14 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
14 | INPUT13 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT13 input was triggered 0: INPUT13 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
13 | INPUT12 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT12 input was triggered 0: INPUT12 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
12 | INPUT11 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT11 input was triggered 0: INPUT11 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
11 | INPUT10 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT10 input was triggered 0: INPUT10 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
10 | INPUT9 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT9 input was triggered 0: INPUT9 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
9 | INPUT8 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT8 input was triggered 0: INPUT8 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
8 | INPUT7 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT7 input was triggered 0: INPUT7 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
7 | ADCSOCB | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCSOCB input was triggered 0: ADCSOCB Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
6 | ADCSOCA | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCSOCA input was triggered 0: ADCSOCA Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
5 | INPUT6 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT6 input was triggered 0: INPUT6 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
4 | INPUT5 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT5 input was triggered 0: INPUT5 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
3 | INPUT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT4 input was triggered 0: INPUT4 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
2 | INPUT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT3 input was triggered 0: INPUT3 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
1 | INPUT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT2 input was triggered 0: INPUT2 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
0 | INPUT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: INPUT1 input was triggered 0: INPUT1 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
XBARFLG3 is shown in Figure 9-26 and described in Table 9-29.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SD1FLT4_DRINT | SD1FLT4_COMPZ | SD1FLT3_DRINT | SD1FLT3_COMPZ | SD1FLT2_DRINT | SD1FLT2_COMPZ | SD1FLT1_DRINT | SD1FLT1_COMPZ |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ECAP7_OUT | SD2FLT4_COMPH | SD2FLT4_COMPL | SD2FLT3_COMPH | SD2FLT3_COMPL | SD2FLT2_COMPH | SD2FLT2_COMPL | SD2FLT1_COMPH |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SD2FLT1_COMPL | SD1FLT4_COMPH | SD1FLT4_COMPL | SD1FLT3_COMPH | SD1FLT3_COMPL | SD1FLT2_COMPH | SD1FLT2_COMPL | SD1FLT1_COMPH |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD1FLT1_COMPL | RESERVED | RESERVED | RESERVED | RESERVED | ADCCEVT4 | ADCCEVT3 | ADCCEVT2 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SD1FLT4_DRINT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT4_DRINT input was triggered 0: SD1FLT4_DRINT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
30 | SD1FLT4_COMPZ | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT4_COMPZ input was triggered 0: SD1FLT4_COMPZ Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
29 | SD1FLT3_DRINT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT3_DRINT input was triggered 0: SD1FLT3_DRINT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
28 | SD1FLT3_COMPZ | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT3_COMPZ input was triggered 0: SD1FLT3_COMPZ Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
27 | SD1FLT2_DRINT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT2_DRINT input was triggered 0: SD1FLT2_DRINT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
26 | SD1FLT2_COMPZ | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT2_COMPZ input was triggered 0: SD1FLT2_COMPZ Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
25 | SD1FLT1_DRINT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT1_DRINT input was triggered 0: SD1FLT1_DRINT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
24 | SD1FLT1_COMPZ | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT1_COMPZ input was triggered 0: SD1FLT1_COMPZ Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
23 | ECAP7_OUT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ECAP7_OUT input was triggered 0: ECAP7_OUT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
22 | SD2FLT4_COMPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT4_COMPH input was triggered 0: SD2FLT4_COMPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
21 | SD2FLT4_COMPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT4_COMPL input was triggered 0: SD2FLT4_COMPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
20 | SD2FLT3_COMPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT3_COMPH input was triggered 0: SD2FLT3_COMPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
19 | SD2FLT3_COMPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT3_COMPL input was triggered 0: SD2FLT3_COMPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
18 | SD2FLT2_COMPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT2_COMPH input was triggered 0: SD2FLT2_COMPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
17 | SD2FLT2_COMPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT2_COMPL input was triggered 0: SD2FLT2_COMPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
16 | SD2FLT1_COMPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT1_COMPH input was triggered 0: SD2FLT1_COMPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
15 | SD2FLT1_COMPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT1_COMPL input was triggered 0: SD2FLT1_COMPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
14 | SD1FLT4_COMPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT4_COMPH input was triggered 0: SD1FLT4_COMPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
13 | SD1FLT4_COMPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT4_COMPL input was triggered 0: SD1FLT4_COMPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
12 | SD1FLT3_COMPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT3_COMPH input was triggered 0: SD1FLT3_COMPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
11 | SD1FLT3_COMPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT3_COMPL input was triggered 0: SD1FLT3_COMPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
10 | SD1FLT2_COMPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT2_COMPH input was triggered 0: SD1FLT2_COMPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
9 | SD1FLT2_COMPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT2_COMPL input was triggered 0: SD1FLT2_COMPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
8 | SD1FLT1_COMPH | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT1_COMPH input was triggered 0: SD1FLT1_COMPH Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
7 | SD1FLT1_COMPL | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD1FLT1_COMPL input was triggered 0: SD1FLT1_COMPL Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | ADCCEVT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCCEVT4 input was triggered 0: ADCCEVT4 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
1 | ADCCEVT3 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCCEVT3 input was triggered 0: ADCCEVT3 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
0 | ADCCEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: ADCCEVT2 input was triggered 0: ADCCEVT2 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
XBARFLG4 is shown in Figure 9-27 and described in Table 9-30.
Return to the Summary Table.
This register is used to flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered.
1: Corresponding Input was triggered
0: Corresponding Input was not triggered
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLAHALT | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLB4_OUT5 | CLB4_OUT4 | CLB3_OUT5 | CLB3_OUT4 | CLB2_OUT5 | CLB2_OUT4 | CLB1_OUT5 | CLB1_OUT4 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | MCANA_FEVT2 | MCANA_FEVT1 | MCANA_FEVT0 | EMAC_PPS0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD2FLT4_DRINT | SD2FLT4_COMPZ | SD2FLT3_DRINT | SD2FLT3_COMPZ | SD2FLT2_DRINT | SD2FLT2_COMPZ | SD2FLT1_DRINT | SD2FLT1_COMPZ |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CLAHALT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLAHALT input was triggered 0: CLAHALT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
30 | RESERVED | R | 0h | Reserved |
29 | RESERVED | R | 0h | Reserved |
28 | RESERVED | R | 0h | Reserved |
27 | RESERVED | R | 0h | Reserved |
26 | RESERVED | R | 0h | Reserved |
25 | RESERVED | R | 0h | Reserved |
24 | RESERVED | R | 0h | Reserved |
23 | CLB4_OUT5 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLB4_OUT5 input was triggered 0: CLB4_OUT5 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
22 | CLB4_OUT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLB4_OUT4 input was triggered 0: CLB4_OUT4 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
21 | CLB3_OUT5 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLB3_OUT5 input was triggered 0: CLB3_OUT5 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
20 | CLB3_OUT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLB3_OUT4 input was triggered 0: CLB3_OUT4 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
19 | CLB2_OUT5 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLB2_OUT5 input was triggered 0: CLB2_OUT5 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
18 | CLB2_OUT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLB2_OUT4 input was triggered 0: CLB2_OUT4 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
17 | CLB1_OUT5 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLB1_OUT5 input was triggered 0: CLB1_OUT5 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
16 | CLB1_OUT4 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: CLB1_OUT4 input was triggered 0: CLB1_OUT4 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | RESERVED | R | 0h | Reserved |
11 | MCANA_FEVT2 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANA_FEVT2 input was triggered 0: MCANA_FEVT2 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
10 | MCANA_FEVT1 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANA_FEVT1 input was triggered 0: MCANA_FEVT1 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
9 | MCANA_FEVT0 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: MCANA_FEVT0 input was triggered 0: MCANA_FEVT0 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
8 | EMAC_PPS0 | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: EMAC_PPS0 input was triggered 0: EMAC_PPS0 Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
7 | SD2FLT4_DRINT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT4_DRINT input was triggered 0: SD2FLT4_DRINT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
6 | SD2FLT4_COMPZ | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT4_COMPZ input was triggered 0: SD2FLT4_COMPZ Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
5 | SD2FLT3_DRINT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT3_DRINT input was triggered 0: SD2FLT3_DRINT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
4 | SD2FLT3_COMPZ | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT3_COMPZ input was triggered 0: SD2FLT3_COMPZ Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
3 | SD2FLT2_DRINT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT2_DRINT input was triggered 0: SD2FLT2_DRINT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
2 | SD2FLT2_COMPZ | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT2_COMPZ input was triggered 0: SD2FLT2_COMPZ Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
1 | SD2FLT1_DRINT | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT1_DRINT input was triggered 0: SD2FLT1_DRINT Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
0 | SD2FLT1_COMPZ | R | 0h | This register is used to Flag the inputs of the X-Bars to provide software knowledge of the input sources which got triggered. 1: SD2FLT1_COMPZ input was triggered 0: SD2FLT1_COMPZ Input was not triggered Note: [1] setting of this bit has priority over clear by software Reset type: CPU1.SYSRSn |
XBARCLR1 is shown in Figure 9-28 and described in Table 9-31.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG1 register.
1: Clears the corresponding bit in the XBARFLG1 register.
0: Writing 0 has no effect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CMPSS8_CTRIPOUTH | CMPSS8_CTRIPOUTL | CMPSS7_CTRIPOUTH | CMPSS7_CTRIPOUTL | CMPSS6_CTRIPOUTH | CMPSS6_CTRIPOUTL | CMPSS5_CTRIPOUTH | CMPSS5_CTRIPOUTL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPSS4_CTRIPOUTH | CMPSS4_CTRIPOUTL | CMPSS3_CTRIPOUTH | CMPSS3_CTRIPOUTL | CMPSS2_CTRIPOUTH | CMPSS2_CTRIPOUTL | CMPSS1_CTRIPOUTH | CMPSS1_CTRIPOUTL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CMPSS8_CTRIPH | CMPSS8_CTRIPL | CMPSS7_CTRIPH | CMPSS7_CTRIPL | CMPSS6_CTRIPH | CMPSS6_CTRIPL | CMPSS5_CTRIPH | CMPSS5_CTRIPL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPSS4_CTRIPH | CMPSS4_CTRIPL | CMPSS3_CTRIPH | CMPSS3_CTRIPL | CMPSS2_CTRIPH | CMPSS2_CTRIPL | CMPSS1_CTRIPH | CMPSS1_CTRIPL |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CMPSS8_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS8_CTRIPOUTH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
30 | CMPSS8_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS8_CTRIPOUTL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
29 | CMPSS7_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS7_CTRIPOUTH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
28 | CMPSS7_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS7_CTRIPOUTL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
27 | CMPSS6_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS6_CTRIPOUTH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
26 | CMPSS6_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS6_CTRIPOUTL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
25 | CMPSS5_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS5_CTRIPOUTH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
24 | CMPSS5_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS5_CTRIPOUTL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
23 | CMPSS4_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS4_CTRIPOUTH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
22 | CMPSS4_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS4_CTRIPOUTL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
21 | CMPSS3_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS3_CTRIPOUTH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
20 | CMPSS3_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS3_CTRIPOUTL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
19 | CMPSS2_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS2_CTRIPOUTH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
18 | CMPSS2_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS2_CTRIPOUTL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
17 | CMPSS1_CTRIPOUTH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS1_CTRIPOUTH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
16 | CMPSS1_CTRIPOUTL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS1_CTRIPOUTL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
15 | CMPSS8_CTRIPH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS8_CTRIPH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
14 | CMPSS8_CTRIPL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS8_CTRIPL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
13 | CMPSS7_CTRIPH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS7_CTRIPH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
12 | CMPSS7_CTRIPL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS7_CTRIPL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
11 | CMPSS6_CTRIPH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS6_CTRIPH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
10 | CMPSS6_CTRIPL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS6_CTRIPL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
9 | CMPSS5_CTRIPH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS5_CTRIPH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
8 | CMPSS5_CTRIPL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS5_CTRIPL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
7 | CMPSS4_CTRIPH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS4_CTRIPH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
6 | CMPSS4_CTRIPL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS4_CTRIPL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
5 | CMPSS3_CTRIPH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS3_CTRIPH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
4 | CMPSS3_CTRIPL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS3_CTRIPL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
3 | CMPSS2_CTRIPH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS2_CTRIPH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
2 | CMPSS2_CTRIPL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS2_CTRIPL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
1 | CMPSS1_CTRIPH | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS1_CTRIPH bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
0 | CMPSS1_CTRIPL | R-0/W1S | 0h | Writing 1 to this bit clears the CMPSS1_CTRIPL bit in the XBARFLG1 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
XBARCLR2 is shown in Figure 9-29 and described in Table 9-32.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG2 register.
1: Clears the corresponding bit in the XBARFLG2 register.
0: Writing 0 has no effect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ADCCEVT1 | ADCBEVT4 | ADCBEVT3 | ADCBEVT2 | ADCBEVT1 | ADCAEVT4 | ADCAEVT3 | ADCAEVT2 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADCAEVT1 | EXTSYNCOUT | ECAP6_OUT | ECAP5_OUT | ECAP4_OUT | ECAP3_OUT | ECAP2_OUT | ECAP1_OUT |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INPUT14 | INPUT13 | INPUT12 | INPUT11 | INPUT10 | INPUT9 | INPUT8 | INPUT7 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADCSOCB | ADCSOCA | INPUT6 | INPUT5 | INPUT4 | INPUT3 | INPUT2 | INPUT1 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ADCCEVT1 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCCEVT1 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
30 | ADCBEVT4 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCBEVT4 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
29 | ADCBEVT3 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCBEVT3 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
28 | ADCBEVT2 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCBEVT2 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
27 | ADCBEVT1 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCBEVT1 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
26 | ADCAEVT4 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCAEVT4 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
25 | ADCAEVT3 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCAEVT3 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
24 | ADCAEVT2 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCAEVT2 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
23 | ADCAEVT1 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCAEVT1 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
22 | EXTSYNCOUT | R-0/W1S | 0h | Writing 1 to this bit clears the EXTSYNCOUT bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
21 | ECAP6_OUT | R-0/W1S | 0h | Writing 1 to this bit clears the ECAP6_OUT bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
20 | ECAP5_OUT | R-0/W1S | 0h | Writing 1 to this bit clears the ECAP5_OUT bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
19 | ECAP4_OUT | R-0/W1S | 0h | Writing 1 to this bit clears the ECAP4_OUT bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
18 | ECAP3_OUT | R-0/W1S | 0h | Writing 1 to this bit clears the ECAP3_OUT bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
17 | ECAP2_OUT | R-0/W1S | 0h | Writing 1 to this bit clears the ECAP2_OUT bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
16 | ECAP1_OUT | R-0/W1S | 0h | Writing 1 to this bit clears the ECAP1_OUT bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
15 | INPUT14 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT14 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
14 | INPUT13 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT13 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
13 | INPUT12 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT12 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
12 | INPUT11 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT11 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
11 | INPUT10 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT10 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
10 | INPUT9 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT9 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
9 | INPUT8 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT8 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
8 | INPUT7 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT7 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
7 | ADCSOCB | R-0/W1S | 0h | Writing 1 to this bit clears the ADCSOCB bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
6 | ADCSOCA | R-0/W1S | 0h | Writing 1 to this bit clears the ADCSOCA bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
5 | INPUT6 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT6 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
4 | INPUT5 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT5 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
3 | INPUT4 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT4 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
2 | INPUT3 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT3 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
1 | INPUT2 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT2 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
0 | INPUT1 | R-0/W1S | 0h | Writing 1 to this bit clears the INPUT1 bit in the XBARFLG2 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
XBARCLR3 is shown in Figure 9-30 and described in Table 9-33.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG3 register.
1: Clears the corresponding bit in the XBARFLG3 register.
0: Writing 0 has no effect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SD1FLT4_DRINT | SD1FLT4_COMPZ | SD1FLT3_DRINT | SD1FLT3_COMPZ | SD1FLT2_DRINT | SD1FLT2_COMPZ | SD1FLT1_DRINT | SD1FLT1_COMPZ |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ECAP7_OUT | SD2FLT4_COMPH | SD2FLT4_COMPL | SD2FLT3_COMPH | SD2FLT3_COMPL | SD2FLT2_COMPH | SD2FLT2_COMPL | SD2FLT1_COMPH |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SD2FLT1_COMPL | SD1FLT4_COMPH | SD1FLT4_COMPL | SD1FLT3_COMPH | SD1FLT3_COMPL | SD1FLT2_COMPH | SD1FLT2_COMPL | SD1FLT1_COMPH |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD1FLT1_COMPL | RESERVED | RESERVED | RESERVED | RESERVED | ADCCEVT4 | ADCCEVT3 | ADCCEVT2 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SD1FLT4_DRINT | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT4_DRINT bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
30 | SD1FLT4_COMPZ | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT4_COMPZ bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
29 | SD1FLT3_DRINT | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT3_DRINT bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
28 | SD1FLT3_COMPZ | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT3_COMPZ bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
27 | SD1FLT2_DRINT | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT2_DRINT bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
26 | SD1FLT2_COMPZ | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT2_COMPZ bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
25 | SD1FLT1_DRINT | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT1_DRINT bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
24 | SD1FLT1_COMPZ | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT1_COMPZ bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
23 | ECAP7_OUT | R-0/W1S | 0h | Writing 1 to this bit clears the ECAP7_OUT bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
22 | SD2FLT4_COMPH | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT4_COMPH bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
21 | SD2FLT4_COMPL | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT4_COMPL bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
20 | SD2FLT3_COMPH | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT3_COMPH bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
19 | SD2FLT3_COMPL | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT3_COMPL bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
18 | SD2FLT2_COMPH | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT2_COMPH bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
17 | SD2FLT2_COMPL | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT2_COMPL bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
16 | SD2FLT1_COMPH | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT1_COMPH bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
15 | SD2FLT1_COMPL | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT1_COMPL bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
14 | SD1FLT4_COMPH | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT4_COMPH bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
13 | SD1FLT4_COMPL | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT4_COMPL bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
12 | SD1FLT3_COMPH | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT3_COMPH bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
11 | SD1FLT3_COMPL | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT3_COMPL bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
10 | SD1FLT2_COMPH | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT2_COMPH bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
9 | SD1FLT2_COMPL | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT2_COMPL bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
8 | SD1FLT1_COMPH | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT1_COMPH bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
7 | SD1FLT1_COMPL | R-0/W1S | 0h | Writing 1 to this bit clears the SD1FLT1_COMPL bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | ADCCEVT4 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCCEVT4 bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
1 | ADCCEVT3 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCCEVT3 bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
0 | ADCCEVT2 | R-0/W1S | 0h | Writing 1 to this bit clears the ADCCEVT2 bit in the XBARFLG3 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
XBARCLR4 is shown in Figure 9-31 and described in Table 9-34.
Return to the Summary Table.
This register is used to clear the flag(s) in the XBARFLG4 register.
1: Clears the corresponding bit in the XBARFLG4 register.
0: Writing 0 has no effect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLAHALT | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLB4_OUT5 | CLB4_OUT4 | CLB3_OUT5 | CLB3_OUT4 | CLB2_OUT5 | CLB2_OUT4 | CLB1_OUT5 | CLB1_OUT4 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SD2FLT4_DRINT | SD2FLT4_COMPZ | SD2FLT3_DRINT | SD2FLT3_COMPZ | SD2FLT2_DRINT | SD2FLT2_COMPZ | SD2FLT1_DRINT | SD2FLT1_COMPZ |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CLAHALT | R | 0h | Writing 1 to this bit clears the CLAHALT bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
30 | RESERVED | R-0/W1S | 0h | Reserved |
29 | RESERVED | R-0/W1S | 0h | Reserved |
28 | RESERVED | R-0/W1S | 0h | Reserved |
27 | RESERVED | R-0/W1S | 0h | Reserved |
26 | RESERVED | R-0/W1S | 0h | Reserved |
25 | RESERVED | R-0/W1S | 0h | Reserved |
24 | RESERVED | R-0/W1S | 0h | Reserved |
23 | CLB4_OUT5 | R-0/W1S | 0h | Writing 1 to this bit clears the CLB4_OUT5 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
22 | CLB4_OUT4 | R-0/W1S | 0h | Writing 1 to this bit clears the CLB4_OUT4 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
21 | CLB3_OUT5 | R-0/W1S | 0h | Writing 1 to this bit clears the CLB3_OUT5 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
20 | CLB3_OUT4 | R-0/W1S | 0h | Writing 1 to this bit clears the CLB3_OUT4 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
19 | CLB2_OUT5 | R-0/W1S | 0h | Writing 1 to this bit clears the CLB2_OUT5 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
18 | CLB2_OUT4 | R-0/W1S | 0h | Writing 1 to this bit clears the CLB2_OUT4 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
17 | CLB1_OUT5 | R-0/W1S | 0h | Writing 1 to this bit clears the CLB1_OUT5 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
16 | CLB1_OUT4 | R-0/W1S | 0h | Writing 1 to this bit clears the CLB1_OUT4 bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
15 | RESERVED | R-0/W1S | 0h | Reserved |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | SD2FLT4_DRINT | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT4_DRINT bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
6 | SD2FLT4_COMPZ | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT4_COMPZ bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
5 | SD2FLT3_DRINT | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT3_DRINT bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
4 | SD2FLT3_COMPZ | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT3_COMPZ bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
3 | SD2FLT2_DRINT | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT2_DRINT bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
2 | SD2FLT2_COMPZ | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT2_COMPZ bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
1 | SD2FLT1_DRINT | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT1_DRINT bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |
0 | SD2FLT1_COMPZ | R-0/W1S | 0h | Writing 1 to this bit clears the SD2FLT1_COMPZ bit in the XBARFLG4 register. Writing 0 has no effect Reset type: CPU1.SYSRSn |