SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 12-5 lists the memory-mapped registers for the ANALOG_SUBSYS_REGS registers. All register offset addresses not listed in Table 12-5 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
1Eh | ANAREFPP | ADC Analog Reference Peripheral Properties register. The value of this register is populated during boot rom. | EALLOW | Go |
60h | TSNSCTL | Temperature Sensor Control Register | EALLOW | Go |
68h | ANAREFCTL | Analog Reference Control Register | EALLOW | Go |
70h | VMONCTL | Voltage Monitor Control Register | EALLOW | Go |
78h | DCDCCTL | DC-DC control register. | EALLOW | Go |
7Ah | DCDCSTS | DC-DC status register. | Go | |
82h | CMPHPMXSEL | Bits to select one of the many sources on CopmHP inputs. Refer to Pimux diagram for details. | EALLOW | Go |
84h | CMPLPMXSEL | Bits to select one of the many sources on CopmLP inputs. Refer to Pimux diagram for details. | EALLOW | Go |
86h | CMPHNMXSEL | Bits to select one of the many sources on CopmHN inputs. Refer to Pimux diagram for details. | EALLOW | Go |
87h | CMPLNMXSEL | Bits to select one of the many sources on CopmLN inputs. Refer to Pimux diagram for details. | EALLOW | Go |
8Eh | LOCK | Lock Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 12-6 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WOnce | W Once | Write Write once |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
ANAREFPP is shown in Figure 12-5 and described in Table 12-7.
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ADC Analog Reference Peripheral Properties register. The value of this register is populated during boot rom.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ANAREFCDIS | ANAREFBDIS | |||||
R-0h | R/WOnce-0h | R/WOnce-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-2 | RESERVED | R | 0h | Reserved |
1 | ANAREFCDIS | R/WOnce | 0h | ANAREFC Disable. This bit field determines, whether ANAREFC is disabled or enabled. 0 ANAREFC is enabled. 1 ANAREFC is disabled. Note: This bit should be programmed to 1 in parts where VREFHIB and VREFHIC are double-bonded. Reset type: XRSn |
0 | ANAREFBDIS | R/WOnce | 0h | ANAREFB Disable. This bit field determines, whether ANAREFB is disabled or enabled. 0 ANAREFB is enabled. 1 ANAREFB is disabled. Note: This bit should be programmed to 1 in parts where VREFHIA, VREFHIB and VREFHIC are triple-bonded. Reset type: XRSn |
TSNSCTL is shown in Figure 12-6 and described in Table 12-8.
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Temperature Sensor Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-1 | RESERVED | R | 0h | Reserved |
0 | ENABLE | R/W | 0h | Temperature Sensor Enable. This bit enables the temperature sensor output to the ADC. 0 Disabled 1 Enabled Reset type: SYSRSn |
ANAREFCTL is shown in Figure 12-7 and described in Table 12-9.
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Analog Reference Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ANAREFC2P5SEL | ANAREFB2P5SEL | ANAREFA2P5SEL | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ANAREFCSEL | ANAREFBSEL | ANAREFASEL | ||||
R-1h | R/W-1h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R | 0h | Reserved |
10 | ANAREFC2P5SEL | R/W | 0h | Analog referenc C 2.5V source select. In internal reference mode, this bit selects which voltage the internal reference buffer drives onto the VREFHI pin. The buffer can drive either 1.65V onto the pin, resulting in a reference range of 0 to 3.3V, or the buffer can drive 2.5V onto the pin, resulting in a reference range of 0 to 2.5V. If switching between these two modes, the user must allow adequate time for the external capacitor to charge to the new voltage before using the ADC or buffered DAC. If multiple VREFHI pins are ganged together (for lower pin-count packages), then the reference voltage select for the ganged pins should always be configured to the same setting. 0 Internal 1.65V reference mode (3.3V reference range) 1 Internal 2.5V reference mode (2.5V reference range) Reset type: XRSn |
9 | ANAREFB2P5SEL | R/W | 0h | Analog referenc B 2.5V source select. In internal reference mode, this bit selects which voltage the internal reference buffer drives onto the VREFHI pin. The buffer can drive either 1.65V onto the pin, resulting in a reference range of 0 to 3.3V, or the buffer can drive 2.5V onto the pin, resulting in a reference range of 0 to 2.5V. If switching between these two modes, the user must allow adequate time for the external capacitor to charge to the new voltage before using the ADC or buffered DAC. If multiple VREFHI pins are ganged together (for lower pin-count packages), then the reference voltage select for the ganged pins should always be configured to the same setting. 0 Internal 1.65V reference mode (3.3V reference range) 1 Internal 2.5V reference mode (2.5V reference range) Reset type: XRSn |
8 | ANAREFA2P5SEL | R/W | 0h | Analog referenc A 2.5V source select. In internal reference mode, this bit selects which voltage the internal reference buffer drives onto the VREFHI pin. The buffer can drive either 1.65V onto the pin, resulting in a reference range of 0 to 3.3V, or the buffer can drive 2.5V onto the pin, resulting in a reference range of 0 to 2.5V. If switching between these two modes, the user must allow adequate time for the external capacitor to charge to the new voltage before using the ADC or buffered DAC. If multiple VREFHI pins are ganged together (for lower pin-count packages), then the reference voltage select for the ganged pins should always be configured to the same setting. 0 Internal 1.65V reference mode (3.3V reference range) 1 Internal 2.5V reference mode (2.5V reference range) Reset type: XRSn |
7-3 | RESERVED | R | 1h | Reserved |
2 | ANAREFCSEL | R/W | 1h | Analog reference C mode select. This bit selects whether the VREFHIC pin uses internal reference mode (the device drives a voltage onto the VREFHI pin) or external reference mode (the system is expected to drive a voltage into the VREFHI pin). If multiple VREFHI pins are ganged together (for lower pin-count packages), then the mode select for the ganged pins should always be configured to the same setting 0 Internal reference mode 1 External reference mode Reset type: XRSn |
1 | ANAREFBSEL | R/W | 1h | Analog reference B mode select. This bit selects whether the VREFHIB pin uses internal reference mode (the device drives a voltage onto the VREFHI pin) or external reference mode (the system is expected to drive a voltage into the VREFHI pin). If multiple VREFHI pins are ganged together (for lower pin-count packages), then the mode select for the ganged pins should always be configured to the same setting 0 Internal reference mode 1 External reference mode Reset type: XRSn |
0 | ANAREFASEL | R/W | 1h | Analog reference A mode select. This bit selects whether the VREFHIA pin uses internal reference mode (the device drives a voltage onto the VREFHI pin) or external reference mode (the system is expected to drive a voltage into the VREFHI pin). If multiple VREFHI pins are ganged together (for lower pin-count packages), then the mode select for the ganged pins should always be configured to the same setting 0 Internal reference mode 1 External reference mode Reset type: XRSn |
VMONCTL is shown in Figure 12-8 and described in Table 12-10.
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Voltage Monitor Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BORLVMONDIS | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R | 0h | Reserved |
8 | BORLVMONDIS | R/W | 0h | BORL disable on VDDIO. 0 BORL is enabled on VDDIO, i.e BOR circuit will be triggered if VDDIO goes lower than the lower BOR threshold of VDDIO. 1 BORL is disabled on VDDIO, i.e BOR circuit will not be triggered if VDDIO goes lower than the lower BOR threshold of VDDIO. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
DCDCCTL is shown in Figure 12-9 and described in Table 12-11.
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DC-DC control register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | ||||||
R/W-1h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCDCEN | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 1h | Reserved |
30-1 | RESERVED | R | 0h | Reserved |
0 | DCDCEN | R/W | 0h | Enable DC-DC. 0 : Disables DC-DC and the device would work of internal VREG. 1 : Enables DC-DC. Reset type: XRSn |
DCDCSTS is shown in Figure 12-10 and described in Table 12-12.
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DC-DC status register.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SWSEQDONE | INDDETECT | ||||
R-0h | R-0h | R-0h | R/W1S-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | SWSEQDONE | R | 0h | DC-DC switch sequence done. 0 : Indicates that the sequence to switch to DC-DC is not complete. 1 : Indicates that the sequence to switch to DC-DC is complete. When DCDCCTL.DCDCEN is set, PMM does the necessary sequencing to switch to DC-DC, and at the end of the sequence this bit will be set. However the power source will be switched to DC-DC only if inductor functionality check passes, else the device will continue to work of VREG. Reset type: XRSn |
0 | INDDETECT | R/W1S | 0h | Inductor Detected Status. 1 : Indicates that the external inductor connected to DC-DC is functional. 0 : Indicates that the external inductor connected to DC-DC is faulty. When DCDCCTL.DCDCEN is set, PMM checks for proper functioning of the external inductor. If the check shows that inductor is functional then this bit will be set. This status of this bit should be checked after DCDCSTS.SWSEQDONE is set. Reset type: XRSn |
CMPHPMXSEL is shown in Figure 12-11 and described in Table 12-13.
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Bits to select one of the many sources on CopmHP inputs. Refer to Pimux diagram for details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CMP7HPMXSEL | CMP6HPMXSEL | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CMP5HPMXSEL | CMP4HPMXSEL | CMP3HPMXSEL | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMP3HPMXSEL | CMP2HPMXSEL | CMP1HPMXSEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R | 0h | Reserved |
21-19 | CMP7HPMXSEL | R/W | 0h | CMP-4HPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
18-16 | CMP6HPMXSEL | R/W | 0h | CMP-5HPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
15 | RESERVED | R | 0h | Reserved |
14-12 | CMP5HPMXSEL | R/W | 0h | CMP5HPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
11-9 | CMP4HPMXSEL | R/W | 0h | CMP4HPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
8-6 | CMP3HPMXSEL | R/W | 0h | CMP3HPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
5-3 | CMP2HPMXSEL | R/W | 0h | CMP2HPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
2-0 | CMP1HPMXSEL | R/W | 0h | CMP1HPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
CMPLPMXSEL is shown in Figure 12-12 and described in Table 12-14.
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Bits to select one of the many sources on CopmLP inputs. Refer to Pimux diagram for details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CMP7LPMXSEL | CMP6LPMXSEL | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CMP5LPMXSEL | CMP4LPMXSEL | CMP3LPMXSEL | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMP3LPMXSEL | CMP2LPMXSEL | CMP1LPMXSEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R | 0h | Reserved |
21-19 | CMP7LPMXSEL | R/W | 0h | CMP7LPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
18-16 | CMP6LPMXSEL | R/W | 0h | CMP6LPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
15 | RESERVED | R | 0h | Reserved |
14-12 | CMP5LPMXSEL | R/W | 0h | CMP5LPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
11-9 | CMP4LPMXSEL | R/W | 0h | CMP4LPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
8-6 | CMP3LPMXSEL | R/W | 0h | CMP3LPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
5-3 | CMP2LPMXSEL | R/W | 0h | CMP2LPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
2-0 | CMP1LPMXSEL | R/W | 0h | CMP1LPMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
CMPHNMXSEL is shown in Figure 12-13 and described in Table 12-15.
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Bits to select one of the many sources on CopmHN inputs. Refer to Pimux diagram for details.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMP7HNMXSEL | CMP6HNMXSEL | CMP5HNMXSEL | CMP4HNMXSEL | CMP3HNMXSEL | CMP2HNMXSEL | CMP1HNMXSEL |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | RESERVED | R | 0h | Reserved |
6 | CMP7HNMXSEL | R/W | 0h | CMP7HNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
5 | CMP6HNMXSEL | R/W | 0h | CMP6HNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
4 | CMP5HNMXSEL | R/W | 0h | CMP5HNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
3 | CMP4HNMXSEL | R/W | 0h | CMP4HNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
2 | CMP3HNMXSEL | R/W | 0h | CMP3HNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
1 | CMP2HNMXSEL | R/W | 0h | CMP2HNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
0 | CMP1HNMXSEL | R/W | 0h | CMP1HNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
CMPLNMXSEL is shown in Figure 12-14 and described in Table 12-16.
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Bits to select one of the many sources on CopmLN inputs. Refer to Pimux diagram for details.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMP7LNMXSEL | CMP6LNMXSEL | CMP5LNMXSEL | CMP4LNMXSEL | CMP3LNMXSEL | CMP2LNMXSEL | CMP1LNMXSEL |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | RESERVED | R | 0h | Reserved |
6 | CMP7LNMXSEL | R/W | 0h | CMP7LNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
5 | CMP6LNMXSEL | R/W | 0h | CMP6LNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
4 | CMP5LNMXSEL | R/W | 0h | CMP5LNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
3 | CMP4LNMXSEL | R/W | 0h | CMP4LNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
2 | CMP3LNMXSEL | R/W | 0h | CMP3LNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
1 | CMP2LNMXSEL | R/W | 0h | CMP2LNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
0 | CMP1LNMXSEL | R/W | 0h | CMP1LNMXSEL bits, Please refer to the analog group connections diagram for the general structure of the CMPSS input mux. Please refer to the Analog Pins and Internal Connections table for specific connections for the CMPSS input mux. Reset type: XRSn |
LOCK is shown in Figure 12-15 and described in Table 12-17.
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Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CMPLNMXSEL | ||||||
R-0h | R/WSonce-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPHNMXSEL | CMPLPMXSEL | CMPHPMXSEL | RESERVED | DCDCCTL | VMONCTL | ANAREFCTL | TSNSCTL |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | CMPLNMXSEL | R/WSonce | 0h | CMPLNMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
7 | CMPHNMXSEL | R/WSonce | 0h | CMPHNMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
6 | CMPLPMXSEL | R/WSonce | 0h | CMPLPMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
5 | CMPHPMXSEL | R/WSonce | 0h | CMPHPMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
4 | RESERVED | R | 0h | Reserved |
3 | DCDCCTL | R/WSonce | 0h | DCDCCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
2 | VMONCTL | R/WSonce | 0h | VMONCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
1 | ANAREFCTL | R/WSonce | 0h | ANAREFCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
0 | TSNSCTL | R/WSonce | 0h | TSNSCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |