SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 3-132 lists the memory-mapped registers for the CPU_SYS_REGS registers. All register offset addresses not listed in Table 3-132 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CPUSYSLOCK1 | Lock bit for CPUSYS registers | EALLOW | Go |
Ah | PIEVERRADDR | PIE Vector Fetch Error Address register | EALLOW | Go |
22h | PCLKCR0 | Peripheral Clock Gating Registers | EALLOW | Go |
26h | PCLKCR2 | Peripheral Clock Gating Registers | EALLOW | Go |
28h | PCLKCR3 | Peripheral Clock Gating Registers | EALLOW | Go |
2Ah | PCLKCR4 | Peripheral Clock Gating Registers | EALLOW | Go |
2Eh | PCLKCR6 | Peripheral Clock Gating Registers | EALLOW | Go |
30h | PCLKCR7 | Peripheral Clock Gating Registers | EALLOW | Go |
32h | PCLKCR8 | Peripheral Clock Gating Registers | EALLOW | Go |
34h | PCLKCR9 | Peripheral Clock Gating Registers | EALLOW | Go |
36h | PCLKCR10 | Peripheral Clock Gating Registers | EALLOW | Go |
3Ch | PCLKCR13 | Peripheral Clock Gating Registers | EALLOW | Go |
3Eh | PCLKCR14 | Peripheral Clock Gating Registers | EALLOW | Go |
40h | PCLKCR15 | Peripheral Clock Gating Registers | EALLOW | Go |
42h | PCLKCR16 | Peripheral Clock Gating Registers | EALLOW | Go |
44h | PCLKCR17 | Peripheral Clock Gating Registers | EALLOW | Go |
46h | PCLKCR18 | Peripheral Clock Gating Registers | EALLOW | Go |
48h | PCLKCR19 | Peripheral Clock Gating Registers | EALLOW | Go |
4Ah | PCLKCR20 | Peripheral Clock Gating Registers | EALLOW | Go |
4Ch | PCLKCR21 | Peripheral Clock Gating Registers | EALLOW | Go |
76h | LPMCR | LPM Control Register | EALLOW | Go |
78h | GPIOLPMSEL0 | GPIO LPM Wakeup select registers | EALLOW | Go |
7Ah | GPIOLPMSEL1 | GPIO LPM Wakeup select registers | EALLOW | Go |
7Ch | TMR2CLKCTL | Timer2 Clock Measurement functionality control register | EALLOW | Go |
7Eh | RESCCLR | Reset Cause Clear Register | Go | |
80h | RESC | Reset Cause register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-133 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CPUSYSLOCK1 is shown in Figure 3-118 and described in Table 3-134.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | PCLKCR21 | PCLKCR20 | PCLKCR19 | PCLKCR18 | PCLKCR17 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIOLPMSEL1 | GPIOLPMSEL0 | LPMCR | RESERVED | PCLKCR16 | PCLKCR15 | PCLKCR14 | PCLKCR13 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | PCLKCR10 | PCLKCR9 | PCLKCR8 | PCLKCR7 | PCLKCR6 | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCLKCR4 | PCLKCR3 | PCLKCR2 | RESERVED | PCLKCR0 | PIEVERRADDR | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/WSonce | 0h | Reserved |
30 | RESERVED | R/WSonce | 0h | Reserved |
29 | RESERVED | R/WSonce | 0h | Reserved |
28 | PCLKCR21 | R/WSonce | 0h | Lock bit for PCLKCR21 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
27 | PCLKCR20 | R/WSonce | 0h | Lock bit for PCLKCR20 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
26 | PCLKCR19 | R/WSonce | 0h | Lock bit for PCLKCR19 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
25 | PCLKCR18 | R/WSonce | 0h | Lock bit for PCLKCR18 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
24 | PCLKCR17 | R/WSonce | 0h | Lock bit for PCLKCR17 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
23 | GPIOLPMSEL1 | R/WSonce | 0h | Lock bit for GPIOLPMSEL1 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
22 | GPIOLPMSEL0 | R/WSonce | 0h | Lock bit for GPIOLPMSEL0 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
21 | LPMCR | R/WSonce | 0h | Lock bit for LPMCR Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
20 | RESERVED | R/WSonce | 0h | Reserved |
19 | PCLKCR16 | R/WSonce | 0h | Lock bit for PCLKCR16 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
18 | PCLKCR15 | R/WSonce | 0h | Lock bit for PCLKCR15 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
17 | PCLKCR14 | R/WSonce | 0h | Lock bit for PCLKCR14 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
16 | PCLKCR13 | R/WSonce | 0h | Lock bit for PCLKCR13 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
15 | RESERVED | R/WSonce | 0h | Reserved |
14 | RESERVED | R/WSonce | 0h | Reserved |
13 | PCLKCR10 | R/WSonce | 0h | Lock bit for PCLKCR10 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
12 | PCLKCR9 | R/WSonce | 0h | Lock bit for PCLKCR9 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
11 | PCLKCR8 | R/WSonce | 0h | Lock bit for PCLKCR8 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
10 | PCLKCR7 | R/WSonce | 0h | Lock bit for PCLKCR7 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
9 | PCLKCR6 | R/WSonce | 0h | Lock bit for PCLKCR6 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
8 | RESERVED | R/WSonce | 0h | Reserved |
7 | PCLKCR4 | R/WSonce | 0h | Lock bit for PCLKCR4 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
6 | PCLKCR3 | R/WSonce | 0h | Lock bit for PCLKCR3 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
5 | PCLKCR2 | R/WSonce | 0h | Lock bit for PCLKCR2 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | PCLKCR0 | R/WSonce | 0h | Lock bit for PCLKCR0 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
2 | PIEVERRADDR | R/WSonce | 0h | Lock bit for PIEVERRADDR Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
1 | RESERVED | R/WSonce | 0h | Reserved |
0 | RESERVED | R/WSonce | 0h | Reserved |
PIEVERRADDR is shown in Figure 3-119 and described in Table 3-135.
Return to the Summary Table.
PIE Vector Fetch Error Address register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||||||||||||||||||||||||||
R-0-0h | R/W-003FFFFFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R-0 | 0h | Reserved |
21-0 | ADDR | R/W | 003FFFFFh | This register defines the address of the PIE Vector Fetch Error handler routine. Its the responsibility of user to initialize this register. If this register is not initialized, a default error handler at address 0x3fffbe will get executed. Refer to the Boot ROM section for more details on this register. Reset type: XRSn |
PCLKCR0 is shown in Figure 3-120 and described in Table 3-136.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | TBCLKSYNC | RESERVED | HRPWM | |||
R-0-0h | R/W-0h | R/W-0h | R-0-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUTIMER2 | CPUTIMER1 | CPUTIMER0 | DMA | RESERVED | CLA1 | |
R-0-0h | R/W-1h | R/W-1h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | TBCLKSYNC | R/W | 0h | EPWM Time Base Clock sync: When set, it synchronizes all enabled ePWM modules to the time-base clock (TBCLK). Reset type: SYSRSn |
17 | RESERVED | R-0 | 0h | Reserved |
16 | HRPWM | R/W | 0h | HRPWM Clock Enable Bit: When set, this enables the clock to the HRPWM module 1: HRPWM clock is enabled 0: HRPWM clock is disabled Reset type: SYSRSn |
15-6 | RESERVED | R-0 | 0h | Reserved |
5 | CPUTIMER2 | R/W | 1h | CPUTIMER2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | CPUTIMER1 | R/W | 1h | CPUTIMER1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | CPUTIMER0 | R/W | 1h | CPUTIMER0 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | DMA | R/W | 0h | DMA Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | CLA1 | R/W | 0h | CLA1 Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR2 is shown in Figure 3-121 and described in Table 3-137.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPWM8 | EPWM7 | EPWM6 | EPWM5 | EPWM4 | EPWM3 | EPWM2 | EPWM1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | EPWM8 | R/W | 0h | EPWM8 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
6 | EPWM7 | R/W | 0h | EPWM7 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
5 | EPWM6 | R/W | 0h | EPWM6 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | EPWM5 | R/W | 0h | EPWM5 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | EPWM4 | R/W | 0h | EPWM4 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | EPWM3 | R/W | 0h | EPWM3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | EPWM2 | R/W | 0h | EPWM2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | EPWM1 | R/W | 0h | EPWM1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR3 is shown in Figure 3-122 and described in Table 3-138.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECAP7 | ECAP6 | ECAP5 | ECAP4 | ECAP3 | ECAP2 | ECAP1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | ECAP7 | R/W | 0h | ECAP7 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
5 | ECAP6 | R/W | 0h | ECAP6 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | ECAP5 | R/W | 0h | ECAP5 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | ECAP4 | R/W | 0h | ECAP4 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | ECAP3 | R/W | 0h | ECAP3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | ECAP2 | R/W | 0h | ECAP2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | ECAP1 | R/W | 0h | ECAP1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR4 is shown in Figure 3-123 and described in Table 3-139.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | EQEP2 | EQEP1 | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | EQEP2 | R/W | 0h | EQEP2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | EQEP1 | R/W | 0h | EQEP1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR6 is shown in Figure 3-124 and described in Table 3-140.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | SD1 | |||||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | SD1 | R/W | 0h | SD1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR7 is shown in Figure 3-125 and described in Table 3-141.
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Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SCI_B | SCI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | SCI_B | R/W | 0h | SCI_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | SCI_A | R/W | 0h | SCI_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR8 is shown in Figure 3-126 and described in Table 3-142.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SPI_B | SPI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | SPI_B | R/W | 0h | SPI_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | SPI_A | R/W | 0h | SPI_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR9 is shown in Figure 3-127 and described in Table 3-143.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | I2C_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | I2C_A | R/W | 0h | I2C_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR10 is shown in Figure 3-128 and described in Table 3-144.
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Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CAN_B | CAN_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | CAN_B | R/W | 0h | CAN_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | CAN_A | R/W | 0h | CAN_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR13 is shown in Figure 3-129 and described in Table 3-145.
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Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ADC_C | ADC_B | ADC_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | ADC_C | R/W | 0h | ADC_C Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | ADC_B | R/W | 0h | ADC_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | ADC_A | R/W | 0h | ADC_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR14 is shown in Figure 3-130 and described in Table 3-146.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMPSS7 | CMPSS6 | CMPSS5 | CMPSS4 | CMPSS3 | CMPSS2 | CMPSS1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | CMPSS7 | R/W | 0h | CMPSS7 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
5 | CMPSS6 | R/W | 0h | CMPSS6 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | CMPSS5 | R/W | 0h | CMPSS5 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | CMPSS4 | R/W | 0h | CMPSS4 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | CMPSS3 | R/W | 0h | CMPSS3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | CMPSS2 | R/W | 0h | CMPSS2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | CMPSS1 | R/W | 0h | CMPSS1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR15 is shown in Figure 3-131 and described in Table 3-147.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PGA7 | PGA6 | PGA5 | PGA4 | PGA3 | PGA2 | PGA1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | PGA7 | R/W | 0h | PGA7 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
5 | PGA6 | R/W | 0h | PGA6 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | PGA5 | R/W | 0h | PGA5 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | PGA4 | R/W | 0h | PGA4 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | PGA3 | R/W | 0h | PGA3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | PGA2 | R/W | 0h | PGA2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | PGA1 | R/W | 0h | PGA1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR16 is shown in Figure 3-132 and described in Table 3-148.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | DAC_B | DAC_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | DAC_B | R/W | 0h | Buffered_DAC_B Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
16 | DAC_A | R/W | 0h | Buffered_DAC_A Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
PCLKCR17 is shown in Figure 3-133 and described in Table 3-149.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLB4 | CLB3 | CLB2 | CLB1 | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | CLB4 | R/W | 0h | CLB4 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | CLB3 | R/W | 0h | CLB3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | CLB2 | R/W | 0h | CLB2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | CLB1 | R/W | 0h | CLB1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR18 is shown in Figure 3-134 and described in Table 3-150.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | FSIRX_A | FSITX_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | FSIRX_A | R/W | 0h | FSIRX_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | FSITX_A | R/W | 0h | FSITX_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR19 is shown in Figure 3-135 and described in Table 3-151.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | LIN_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | LIN_A | R/W | 0h | LIN_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR20 is shown in Figure 3-136 and described in Table 3-152.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | PMBUS_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | PMBUS_A | R/W | 0h | PMBUS_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR21 is shown in Figure 3-137 and described in Table 3-153.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCC_0 | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | DCC_0 | R/W | 0h | DCC Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
LPMCR is shown in Figure 3-138 and described in Table 3-154.
Return to the Summary Table.
LPM Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | ||||||
R/W1S-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | ||||||
R/W-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LPM | ||||||
R/W-3Fh | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W1S | 0h | Reserved |
30-18 | RESERVED | R-0 | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14-8 | RESERVED | R-0 | 0h | Reserved |
7-2 | RESERVED | R/W | 3Fh | Reserved |
1-0 | LPM | R/W | 0h | These bits set the low power mode for the device. Takes effect when CPU executes the IDLE instruction (when IDLE instruction is out of EXE Phase of the Pipeline) 00: IDLE Mode 01: Reserved 1x: HALT Mode Reset type: SYSRSn |
GPIOLPMSEL0 is shown in Figure 3-139 and described in Table 3-155.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the selected pin.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO27 | GPIO26 | GPIO25 | GPIO24 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO15 | GPIO14 | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | GPIO31 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
30 | GPIO30 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
29 | GPIO29 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
28 | GPIO28 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
27 | GPIO27 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
26 | GPIO26 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
25 | GPIO25 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
24 | GPIO24 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
23 | GPIO23 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
22 | GPIO22 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
21 | GPIO21 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
20 | GPIO20 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
19 | GPIO19 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
18 | GPIO18 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
17 | GPIO17 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
16 | GPIO16 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
15 | GPIO15 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
14 | GPIO14 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
13 | GPIO13 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
12 | GPIO12 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
11 | GPIO11 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
10 | GPIO10 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
9 | GPIO9 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
8 | GPIO8 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
7 | GPIO7 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
6 | GPIO6 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
5 | GPIO5 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
4 | GPIO4 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
3 | GPIO3 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
2 | GPIO2 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
1 | GPIO1 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
0 | GPIO0 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
GPIOLPMSEL1 is shown in Figure 3-140 and described in Table 3-156.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the selected pin.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
GPIO63 | GPIO62 | GPIO61 | GPIO60 | GPIO59 | GPIO58 | GPIO57 | GPIO56 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO55 | GPIO54 | GPIO53 | GPIO52 | GPIO51 | GPIO50 | GPIO49 | GPIO48 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO47 | GPIO46 | GPIO45 | GPIO44 | GPIO43 | GPIO42 | GPIO41 | GPIO40 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | GPIO38 | GPIO37 | GPIO36 | GPIO35 | GPIO34 | GPIO33 | GPIO32 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | GPIO63 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
30 | GPIO62 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
29 | GPIO61 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
28 | GPIO60 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
27 | GPIO59 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
26 | GPIO58 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
25 | GPIO57 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
24 | GPIO56 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
23 | GPIO55 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
22 | GPIO54 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
21 | GPIO53 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
20 | GPIO52 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
19 | GPIO51 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
18 | GPIO50 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
17 | GPIO49 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
16 | GPIO48 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
15 | GPIO47 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
14 | GPIO46 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
13 | GPIO45 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
12 | GPIO44 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
11 | GPIO43 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
10 | GPIO42 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
9 | GPIO41 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
8 | GPIO40 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
7 | GPIO39 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
6 | GPIO38 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
5 | GPIO37 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
4 | GPIO36 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
3 | GPIO35 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
2 | GPIO34 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
1 | GPIO33 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
0 | GPIO32 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
TMR2CLKCTL is shown in Figure 3-141 and described in Table 3-157.
Return to the Summary Table.
Timer2 Clock Measurement functionality control register
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TMR2CLKPRESCALE | TMR2CLKSRCSEL | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5-3 | TMR2CLKPRESCALE | R/W | 0h | CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale value for the selected clock source for CPU Timer 2: 0,0,0,/1 (default on reset) 0,0,1,/2, 0,1,0,/4 0,1,1,/8 1,0,0,/16 1,0,1,spare (defaults to /16) 1,1,0,spare (defaults to /16) 1,1,1,spare (defaults to /16) Note: [1] The CPU Timer2s Clock sync logic detects an input clock edge when configured for any clock source other than SYSCLK and generates an appropriate clock pulse to the CPU timer2. If SYSCLK is approximately the same or less then the input clock source, then the user would need to configure the pre-scale value such that SYSCLK is at least twice as fast as the pre-scaled value. Reset type: SYSRSn |
2-0 | TMR2CLKSRCSEL | R/W | 0h | CPU Timer 2 Clock Source Select Bit: This bit selects the source for CPU Timer 2: 000 =SYSCLK Selected (default on reset, pre-scale is bypassed) 001 = INTOSC1 010 = INTOSC2 011 = XTAL 100 = FLPUMPOSC 101 = FOSCCLK 110 = AUXPLLCLK (Reserved) 111 = reserved Reset type: SYSRSn |
RESCCLR is shown in Figure 3-142 and described in Table 3-158.
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Reset Cause Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SCCRESETn | ||||||
R-0-0h | W1S-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | NMIWDRSn | WDRSn | XRSn | POR |
R-0-0h | W1S-0h | W1S-0h | R-0-0h | W1S-0h | W1S-0h | W1S-0h | W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R-0 | 0h | Reserved |
8 | SCCRESETn | W1S | 0h | Clear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0. Writing a 1 to this bit clears the status bit in RESC to 0 Writing 0 has no effect. Reset type: SYSRSn |
7 | RESERVED | R-0 | 0h | Reserved |
6 | RESERVED | W1S | 0h | Reserved |
5 | RESERVED | W1S | 0h | Reserved |
4 | RESERVED | R-0 | 0h | Reserved |
3 | NMIWDRSn | W1S | 0h | Clear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0. Writing a 1 to this bit clears the status bit in RESC to 0 Writing 0 has no effect. Reset type: SYSRSn |
2 | WDRSn | W1S | 0h | Clear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0. Writing a 1 to this bit clears the status bit in RESC to 0 Writing 0 has no effect. Reset type: SYSRSn |
1 | XRSn | W1S | 0h | Clear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0. Writing a 1 to this bit clears the status bit in RESC to 0 Writing 0 has no effect. Reset type: SYSRSn |
0 | POR | W1S | 0h | Clear bit for corresponding status bit in RESC. Read of RESCCLR always gives 0. Writing a 1 to this bit clears the status bit in RESC to 0 Writing 0 has no effect. Reset type: SYSRSn |
RESC is shown in Figure 3-143 and described in Table 3-159.
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Reset Cause register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DCON | XRSn_pin_status | RESERVED | |||||
R-0h | R-X | R-0-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SCCRESETn | ||||||
R-0-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | NMIWDRSn | WDRSn | XRSn | POR |
R-0-0h | R-0h | R-0h | R-0-0h | R-0h | R-0h | R-1h | R-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | DCON | R | 0h | Reading this bit provides the status of debugger connection to the C28x CPU. 0 : Debugger is not connected to the C28x CPU 1 : Debugger is connected to the C28x CPU Notes: [1] This bit is connected to the DCON o/p signal of the C28x CPU Reset type: N/A |
30 | XRSn_pin_status | R | X | Reading this bit provides the current status of the XRSn pin. Reset value is reflective of the pin status. Reset type: N/A |
29-9 | RESERVED | R-0 | 0h | Reserved |
8 | SCCRESETn | R | 0h | If this bit is set, indicates that the device was reset by SCCRESETn (fired by DCSM). Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: POR |
7 | RESERVED | R-0 | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R-0 | 0h | Reserved |
3 | NMIWDRSn | R | 0h | If this bit is set, indicates that the device was reset by NMIWDRSn. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. To know the exact cause of NMI after the reset, software needs to read CPU1.NMISHDFLG registers Reset type: POR |
2 | WDRSn | R | 0h | If this bit is set, indicates that the device was reset by WDRSn. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Note: [1] A bit inside WD module also provides the same information. This bit is present to keep things consistent. This register is a one-stop shop for the software to know the reset cause for the C28x core. Reset type: POR |
1 | XRSn | R | 1h | If this bit is set, indicates that the device was reset by XRSn. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: POR |
0 | POR | R | 1h | If this bit is set, indicates that the device was reset by POR/BOR. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: POR |