SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 3-63 lists the memory-mapped registers for the NMI_INTRUPT_REGS registers. All register offset addresses not listed in Table 3-63 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | NMICFG | NMI Configuration Register | EALLOW | Go |
1h | NMIFLG | NMI Flag Register (SYSRsn Clear) | Go | |
2h | NMIFLGCLR | NMI Flag Clear Register | EALLOW | Go |
3h | NMIFLGFRC | NMI Flag Force Register | EALLOW | Go |
4h | NMIWDCNT | NMI Watchdog Counter Register | Go | |
5h | NMIWDPRD | NMI Watchdog Period Register | EALLOW | Go |
6h | NMISHDFLG | NMI Shadow Flag Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-64 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value |
NMICFG is shown in Figure 3-59 and described in Table 3-65.
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NMI Configuration Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NMIE | ||||||
R-0-0h | R/W1S-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-1 | RESERVED | R-0 | 0h | Reserved |
0 | NMIE | R/W1S | 0h | Global NMI Enable This bit indicates that the NMI module has been enabled, which allows system error conditions to trigger an NMI to the CPU. The boot ROM sets this bit at start-up. It can only be cleared by a system reset. Reset type: SYSRSn |
NMIFLG is shown in Figure 3-60 and described in Table 3-66.
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NMI Flag Register (SYSRsn Clear)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SWERR | RESERVED | RESERVED | RESERVED | RESERVED | CLBNMI | |
R-0-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PIEVECTERR | RESERVED | RESERVED | FLUNCERR | RAMUNCERR | CLOCKFAIL | NMIINT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R-0 | 0h | Reserved |
13 | SWERR | R | 0h | Software-Forced NMI Flag This bit can only be set by writing to the corresponding bit in the NMIFLGFRC register. It can be cleared by a system reset or by writing to the corresponding bit in the NMIFLGCLR register. No further NMIs are generated until this flag is cleared. Reset type: SYSRSn 0h (R/W) = No software NMI forced 1h (R/W) = Software NMI forced |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | CLBNMI | R | 0h | CLB NMI Flag This bit indicates whether an NMI was generated by the CLB. It can be cleared by a system reset or by writing to the corresponding bit in the NMIFLGCLR register. Reset type: SYSRSn 0h (R/W) = No CLB NMI generated 1h (R/W) = CLB NMI generated |
7 | RESERVED | R | 0h | Reserved |
6 | PIEVECTERR | R | 0h | PIE Vector Fetch Error NMI Flag This bit indicates whether a mismatch was detected during an interrupt vector fetch. It can be cleared by a system reset or by writing to the corresponding bit in the NMIFLGCLR register. Reset type: SYSRSn 0h (R/W) = No vector fetch error detected 1h (R/W) = Vector fetch error detected |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | FLUNCERR | R | 0h | Flash Uncorrectable Error NMI Flag This bit indicates whether an uncorrectable ECC error occurred during a flash access. It can be cleared by a system reset or by writing to the corresponding bit in the NMIFLGCLR register. Reset type: SYSRSn 0h (R/W) = No uncorrectable error detected 1h (R/W) = Uncorrectable error detected |
2 | RAMUNCERR | R | 0h | RAM Uncorrectable Error NMI Flag This bit indicates whether an uncorrectable ECC error has occurred during a RAM access by any master. It can be cleared by a system reset or by writing to the corresponding bit in the NMIFLGCLR register. Reset type: SYSRSn 0h (R/W) = No uncorrectable error detected 1h (R/W) = Uncorrectable error detected |
1 | CLOCKFAIL | R | 0h | Clock Fail NMI Flag This bit indicates whether a clock fail condition has been detected. It can be cleared by a system reset or by writing to the corresponding bit in the NMIFLGCLR register. Reset type: SYSRSn 0h (R/W) = No clock fail detected 1h (R/W) = Clock fail detected |
0 | NMIINT | R | 0h | Global NMI Flag This bit indicates whether an NMI has been generated. It can be cleared by a system reset or by writing to the corresponding bit in the NMIFLGCLR register. No further NMIs are generated until this flag is cleared. Reset type: SYSRSn 0h (R/W) = No NMI generated 1h (R/W) = NMI generated |
NMIFLGCLR is shown in Figure 3-61 and described in Table 3-67.
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Writing a 1 to one of these bits clears the corresponding bit in the NMIFLG register. Writes of 0 are ignored, and these bits always read 0. If an NMI arrives on the same cycle that this register is written, the NMI is latched. All other NMI flags must be cleared before the NMIINT flag is cleared, otherwise NMIINT will be set again.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SWERR | RESERVED | RESERVED | RESERVED | RESERVED | CLBNMI | |
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PIEVECTERR | RESERVED | RESERVED | FLUNCERR | RAMUNCERR | CLOCKFAIL | NMIINT |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R-0 | 0h | Reserved |
13 | SWERR | R-0/W1S | 0h | Clear the SWERR flag. Reset type: SYSRSn |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | CLBNMI | R-0/W1S | 0h | Clear the CLBNMI flag. Reset type: SYSRSn |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | PIEVECTERR | R-0/W1S | 0h | Clear the PIEVECTERR flag. Reset type: SYSRSn |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | FLUNCERR | R-0/W1S | 0h | Clear the FLUNCERR flag. Reset type: SYSRSn |
2 | RAMUNCERR | R-0/W1S | 0h | Clear the RAMUNCERR flag. Reset type: SYSRSn |
1 | CLOCKFAIL | R-0/W1S | 0h | Clear the CLOCKFAIL flag. Reset type: SYSRSn |
0 | NMIINT | R-0/W1S | 0h | Clear the NMIINT flag. This flag should only be cleared after all other active flags have been cleared. Reset type: SYSRSn |
NMIFLGFRC is shown in Figure 3-62 and described in Table 3-68.
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Writing a 1 to one of these bits sets the corresponding bit in the NMIFLG register. Writes of 0 are ignored, and these bits always read 0. This register can be used to test the NMI functionality.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SWERR | RESERVED | RESERVED | RESERVED | RESERVED | CLBNMI | |
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PIEVECTERR | RESERVED | RESERVED | FLUNCERR | RAMUNCERR | CLOCKFAIL | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R-0 | 0h | Reserved |
13 | SWERR | R-0/W1S | 0h | Set the SWERR flag. Reset type: SYSRSn |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | CLBNMI | R-0/W1S | 0h | Set the CLBNMI flag. Reset type: SYSRSn |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | PIEVECTERR | R-0/W1S | 0h | Set the PIEVECTERR flag. Reset type: SYSRSn |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | FLUNCERR | R-0/W1S | 0h | Set the FLUNCERR flag. Reset type: SYSRSn |
2 | RAMUNCERR | R-0/W1S | 0h | Set the RAMUNCERR flag. Reset type: SYSRSn |
1 | CLOCKFAIL | R-0/W1S | 0h | Set the CLOCKFAIL flag. Reset type: SYSRSn |
0 | RESERVED | R-0 | 0h | Reserved |
NMIWDCNT is shown in Figure 3-63 and described in Table 3-69.
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NMI Watchdog Counter Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMIWDCNT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMIWDCNT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | NMIWDCNT | R | 0h | NMI Watchdog Counter This 16-bit counter increments once per SYSCLK cycle whenever any of the NMIFLG bits are set. If the counter reaches the period value in the NMIWDPRD register, the NMI module generates a reset (NMIWDRS). After this reset, the counter resets to zero and stops counting. If all NMI flags are cleared, the counter will reset to zero and stop counting until another NMI flag is set. Reset type: SYSRSn |
NMIWDPRD is shown in Figure 3-64 and described in Table 3-70.
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NMI Watchdog Period Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMIWDPRD | |||||||
R/W-FFFFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMIWDPRD | |||||||
R/W-FFFFh | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | NMIWDPRD | R/W | FFFFh | NMI Watchdog Period These bits specify the period of the NMI watchdog timer in SYSCLK cycles. Writing a period value that is smaller than the current counter value will immediately force a reset (NMIWDRS). Reset type: SYSRSn |
NMISHDFLG is shown in Figure 3-65 and described in Table 3-71.
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These shadow flag bits are set whenever the corresponding bits in the NMIFLG register are set. The shadow flags are only reset by a power-on reset (POR), but any system or external reset will reset the normal flags. The shadow flags allow NMIs to be tracked across resets.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SWERR | RESERVED | RESERVED | RESERVED | RESERVED | CLBNMI | |
R-0-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PIEVECTERR | RESERVED | RESERVED | FLUNCERR | RAMUNCERR | CLOCKFAIL | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-14 | RESERVED | R-0 | 0h | Reserved |
13 | SWERR | R | 0h | Shadow SWERR flag Reset type: PORESETn |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | CLBNMI | R | 0h | Shadow CLBNMI flag Reset type: PORESETn |
7 | RESERVED | R | 0h | Reserved |
6 | PIEVECTERR | R | 0h | Shadow PIEVECTERR flag Reset type: PORESETn |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | FLUNCERR | R | 0h | Shadow FLUNCERR flag Reset type: PORESETn |
2 | RAMUNCERR | R | 0h | Shadow RAMUNCERR flag Reset type: PORESETn |
1 | CLOCKFAIL | R | 0h | Shadow CLOCKFAIL flag Reset type: PORESETn |
0 | RESERVED | R-0 | 0h | Reserved |