SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 3-117 lists the memory-mapped registers for the CLK_CFG_REGS registers. All register offset addresses not listed in Table 3-117 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
2h | CLKCFGLOCK1 | Lock bit for CLKCFG registers | EALLOW | Go |
8h | CLKSRCCTL1 | Clock Source Control register-1 | EALLOW | Go |
Ah | CLKSRCCTL2 | Clock Source Control register-2 | EALLOW | Go |
Ch | CLKSRCCTL3 | Clock Source Control register-3 | EALLOW | Go |
Eh | SYSPLLCTL1 | SYSPLL Control register-1 | EALLOW | Go |
14h | SYSPLLMULT | SYSPLL Multiplier register | EALLOW | Go |
16h | SYSPLLSTS | SYSPLL Status register | Go | |
22h | SYSCLKDIVSEL | System Clock Divider Select register | EALLOW | Go |
28h | XCLKOUTDIVSEL | XCLKOUT Divider Select register | EALLOW | Go |
2Ch | LOSPCP | Low Speed Clock Source Prescalar | EALLOW | Go |
2Eh | MCDCR | Missing Clock Detect Control Register | EALLOW | Go |
30h | X1CNT | 10-bit Counter on X1 Clock | Go | |
32h | XTALCR | XTAL Control Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-118 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CLKCFGLOCK1 is shown in Figure 3-105 and described in Table 3-119.
Return to the Summary Table.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | XTALCR | ||||||
R-0-0h | R/WSonce-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOSPCP | RESERVED | RESERVED | RESERVED | SYSCLKDIVSEL | RESERVED | RESERVED | RESERVED |
R/WSonce-0h | R-0-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R-0-0h | R-0-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYSPLLMULT | RESERVED | RESERVED | SYSPLLCTL1 | CLKSRCCTL3 | CLKSRCCTL2 | CLKSRCCTL1 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R-0 | 0h | Reserved |
16 | XTALCR | R/WSonce | 0h | Lock bit for XTALCR register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
15 | LOSPCP | R/WSonce | 0h | Lock bit for LOSPCP register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
14 | RESERVED | R-0 | 0h | Reserved |
13 | RESERVED | R/WSonce | 0h | Reserved |
12 | RESERVED | R/WSonce | 0h | Reserved |
11 | SYSCLKDIVSEL | R/WSonce | 0h | Lock bit for SYSCLKDIVSEL register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
10 | RESERVED | R/WSonce | 0h | Reserved |
9 | RESERVED | R-0 | 0h | Reserved |
8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/WSonce | 0h | Reserved |
6 | SYSPLLMULT | R/WSonce | 0h | Lock bit for SYSPLLMULT register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
5 | RESERVED | R/WSonce | 0h | Reserved |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | SYSPLLCTL1 | R/WSonce | 0h | Lock bit for SYSPLLCTL1 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
2 | CLKSRCCTL3 | R/WSonce | 0h | Lock bit for CLKSRCCTL3 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
1 | CLKSRCCTL2 | R/WSonce | 0h | Lock bit for CLKSRCCTL2 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
0 | CLKSRCCTL1 | R/WSonce | 0h | Lock bit for CLKSRCCTL1 register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
CLKSRCCTL1 is shown in Figure 3-106 and described in Table 3-120.
Return to the Summary Table.
Clock Source Control register-1
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDHALTI | RESERVED | INTOSC2OFF | RESERVED | OSCCLKSRCSEL | ||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R-0-0h | R/W-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5 | WDHALTI | R/W | 0h | Watchdog HALT Mode Ignore Bit: This bit determines if WD is functional in the HALT mode or not. 0 = WD is not functional in the HALT mode. Clock to WD is gated when system enters HALT mode. Additionally, INTOSC1 and INTOSC2 are powered-down when system enters HALT mode 1 = WD is functional in the HALT mode. Clock to WD is not gated and INTOSC1/2 are not powered-down when system enters HALT mode Reset type: XRSn |
4 | RESERVED | R/W | 0h | Reserved |
3 | INTOSC2OFF | R/W | 0h | Internal Oscillator 2 Off Bit: This bit turns oscillator 2 off: 0 = Internal Oscillator 2 On (default on reset) 1 = Internal Oscillator 2 Off This bit could be used by the user to turn off the internal oscillator 2 if it is not used. NOTE: Ensure no resources are using a clock source prior to disabling it. For example OSCCLKSRCSEL (SYSPLL), AUXOSCCLKSRCSEL (AUXPLL), TMR2CLKSRCSEL (CPUTIMER2) and XCLOCKOUT (XCLKOUT). Reset type: XRSn |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | OSCCLKSRCSEL | R/W | 0h | Oscillator Clock Source Select Bit: This bit selects the source for OSCCLK. 00 = INTOSC2 (default on reset) 01 = External Oscillator (XTAL) 10 = INTOSC1 11 = reserved (default to INTOSC1) At power-up or after an XRSn, INTOSC2 is selected by default. Whenever the user changes the clock source using these bits, the SYSPLLMULT register will be forced to zero and the PLL will be bypassed and powered down. This prevents potential PLL overshoot. The user will then have to write to the SYSPLLMULT register to configure the appropriate multiplier. The user must wait 10 OSCCLK cycles before writing to SYSPLLMULT or disabling the previous clock source to allow the change to complete.. Notes: [1] Reserved selection defaults to 00 configuration [2] INTOSC1 is recommended to be used only after missing clock detection. If user wants to re-lock the PLL with INTOSC1 (the back-up clock source) after missing clock is detected, he can do a MCLKCLR and lock the PLL. Reset type: XRSn |
CLKSRCCTL2 is shown in Figure 3-107 and described in Table 3-121.
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Clock Source Control register-2
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CANBBCLKSEL | CANABCLKSEL | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R-0 | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | CANBBCLKSEL | R/W | 0h | CANB Bit-Clock Source Select Bit: 00 = PERx.SYSCLK (default on reset) 01 = External Oscillator (XTAL) 10 = Reserved 11 = Reserved Missing clock detect circuit doesnt have any impact on these bits. Reset type: XRSn |
3-2 | CANABCLKSEL | R/W | 0h | CANA Bit-Clock Source Select Bit: 00 = PERx.SYSCLK (default on reset) 01 = External Oscillator (XTAL) 10 = Reserved 11 = Reserved Missing clock detect circuit doesnt have any impact on these bits. Reset type: XRSn |
1-0 | RESERVED | R/W | 0h | Reserved |
CLKSRCCTL3 is shown in Figure 3-108 and described in Table 3-122.
Return to the Summary Table.
Clock Source Control register-3
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XCLKOUTSEL | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R-0 | 0h | Reserved |
2-0 | XCLKOUTSEL | R/W | 0h | XCLKOUT Source Select Bit: This bit selects the source for XCLKOUT: 000 = PLLSYSCLK (default on reset) 001 = PLLRAWCLK 010 = SYSCLK 011 = Reserved 100 = Reserved 101 = INTOSC1 110 = INTOSC2 111 = XTAL OSC o/p clock Reset type: SYSRSn |
SYSPLLCTL1 is shown in Figure 3-109 and described in Table 3-123.
Return to the Summary Table.
SYSPLL Control register-1
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLLCLKEN | PLLEN | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | PLLCLKEN | R/W | 0h | SYSPLL bypassed or included in the PLLSYSCLK path: This bit decides if the SYSPLL is bypassed when PLLSYSCLK is generated 1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need to make sure that the PLL is locked before enabling this clock to the system. 0 = SYSPLL is bypassed. Clock to system is direct feed from OSCCLK Reset type: XRSn |
0 | PLLEN | R/W | 0h | SYSPLL enabled or disabled: This bit decides if the SYSPLL is enabled or not 1 = SYSPLL is enabled 0 = SYSPLL is powered off. Clock to system is direct feed from OSCCLK Reset type: XRSn |
SYSPLLMULT is shown in Figure 3-110 and described in Table 3-124.
Return to the Summary Table.
SYSPLL Multiplier register
NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ODIV | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FMULT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IMULT | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R-0 | 0h | Reserved |
29-24 | RESERVED | R/W | 0h | Reserved |
23-19 | RESERVED | R-0 | 0h | Reserved |
18-16 | ODIV | R/W | 0h | SYSPLL Output Clock Divider PLL Output Divider = ODIV + 1 Reset type: XRSn |
15-10 | RESERVED | R-0 | 0h | Reserved |
9-8 | FMULT | R/W | 0h | SYSPLL Fractional Multiplier: 00 Fractional Multiplier = 0 01 Fractional Multiplier = 0.25 10 Fractional Multiplier = 0.5 11 Fractional Multiplier = 0.75 Reset type: XRSn |
7 | RESERVED | R-0 | 0h | Reserved |
6-0 | IMULT | R/W | 0h | SYSPLL Integer Multiplier: For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1 0000001 Integer Multiplier = 1 0000010 Integer Multiplier = 2 0000011 Integer Multiplier = 3 ....... 1111111 Integer Multipler = 127 Reset type: XRSn |
SYSPLLSTS is shown in Figure 3-111 and described in Table 3-125.
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SYSPLL Status register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLIPS | LOCKS | |||||
R-0-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | SLIPS | R | 0h | SYSPLL Slip Status Bit: This bit indicates whether the SYSPLL is out of lock range 0 = SYSPLL is not out of lock 1 = SYSPLL is out of lock Reset type: XRSn |
0 | LOCKS | R | 0h | SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is locked or not 0 = SYSPLL is not yet locked 1 = SYSPLL is locked Reset type: XRSn |
SYSCLKDIVSEL is shown in Figure 3-112 and described in Table 3-126.
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System Clock Divider Select register
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLLSYSCLKDIV | ||||||||||||||
R-0-0h | R/W-2h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5-0 | PLLSYSCLKDIV | R/W | 2h | PLLSYSCLK Divide Select: This bit selects the divider setting for the PLLSYSCLK. 000000 = /1 000001 = /2 000010 = /4 (default on reset) 000011 = /6 000100 = /8 ...... 111111 = /126 Reset type: XRSn |
XCLKOUTDIVSEL is shown in Figure 3-113 and described in Table 3-127.
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XCLKOUT Divider Select register
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XCLKOUTDIV | ||||||
R-0-0h | R/W-3h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | XCLKOUTDIV | R/W | 3h | XCLKOUT Divide Select: This bit selects the divider setting for the XCLKOUT. 00 = /1 01 = /2 10 = /4 11 = /8 (default on reset) Reset type: SYSRSn |
LOSPCP is shown in Figure 3-114 and described in Table 3-128.
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Low Speed Clock Source Prescalar
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LSPCLKDIV | ||||||||||||||
R-0-0h | R/W-2h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R-0 | 0h | Reserved |
2-0 | LSPCLKDIV | R/W | 2h | These bits configure the low-speed peripheral clock (LSPCLK) rate 000,LSPCLK = / 1 001,LSPCLK = / 2 010,LSPCLK = / 4 (default on reset) 011,LSPCLK = / 6 100,LSPCLK = / 8 101,LSPCLK = / 10 110,LSPCLK = / 12 111,LSPCLK = / 14 Note: [1] This clock is used as strobe for the SCI and SPI modules. Reset type: SYSRSn |
MCDCR is shown in Figure 3-115 and described in Table 3-129.
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Missing Clock Detect Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OSCOFF | MCLKOFF | MCLKCLR | MCLKSTS | |||
R-0-0h | R/W-0h | R/W-0h | R-0/W1S-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | OSCOFF | R/W | 0h | Oscillator Clock Disconnect from MCD Bit: 0 = OSCCLK Connected to OSCCLK Counter in MCD module 1 = OSCCLK Disconnected to OSCCLK Counter in MCD module Reset type: XRSn |
2 | MCLKOFF | R/W | 0h | Missing Clock Detect Off Bit: 0 = Missing Clock Detect Circuit Enabled 1 = Missing Clock Detect Circuit Disabled Reset type: XRSn |
1 | MCLKCLR | R-0/W1S | 0h | Missing Clock Clear Bit: Write 1' to this bit to clear MCLKSTS bit and reset the missing clock detect circuit.' Reset type: XRSn |
0 | MCLKSTS | R | 0h | Missing Clock Status Bit: 0 = OSCCLK Is OK 1 = OSCCLK Detected Missing, CLOCKFAILn Generated Reset type: XRSn |
X1CNT is shown in Figure 3-116 and described in Table 3-130.
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10-bit Counter on X1 Clock
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CLR | ||||||||||||||
R-0-0h | R-0/W1S-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | X1CNT | ||||||||||||||
R-0-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R-0 | 0h | Reserved |
16 | CLR | R-0/W1S | 0h | X1 Counter clear: A write of '1' to this bit field clears the X1CNT and makes it count from 0x0 again (provided X1 clock is ticking). Writes of '0' are ignore to this bit field Reset type: N/A |
15-10 | RESERVED | R-0 | 0h | Reserved |
9-0 | X1CNT | R | 0h | X1 Counter: - This counter increments on every X1 CLOCKs positive-edge. - Once it reaches the values of 0x3ff, it freezes - Before switching from INTOSC2 to X1, application must check this counter and make sure that it has saturated. This will ensure that the Crystal connected to X1/X2 is oscillating. Reset type: POR |
XTALCR is shown in Figure 3-117 and described in Table 3-131.
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XTAL Control Register
This memory mapped register requires a delay of 39 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 39 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SE | OSCOFF | ||||
R-0-0h | R/W-1h | R/W-0h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R/W | 1h | Reserved |
1 | SE | R/W | 0h | Configures XTAL oscillator in single-ended or Crystal mode when XTAL oscillator is powered up(i.e. OSCOFF = 0) 0 XTAL oscillator in Crystal mode 1 XTAL oscilator in single-ended mode (through X1) Reset type: XRSn |
0 | OSCOFF | R/W | 1h | This bit if '1', powers-down the XTAL oscillator macro and hence doesn't let X2 to be driven by the XTAL oscillator. If a crystal is connected to X1/X2, user needs to first clear this bit, wait for the oscillator to power up (using X1CNT) and then only switch the clock source to X1/X2 Reset type: XRSn |