SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 3-318 lists the memory-mapped registers for the MEMORY_ERROR_REGS registers. All register offset addresses not listed in Table 3-318 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | UCERRFLG | Uncorrectable Error Flag Register | Go | |
2h | UCERRSET | Uncorrectable Error Flag Set Register | EALLOW | Go |
4h | UCERRCLR | Uncorrectable Error Flag Clear Register | EALLOW | Go |
6h | UCCPUREADDR | Uncorrectable CPU Read Error Address | Go | |
8h | UCDMAREADDR | Uncorrectable DMA Read Error Address | Go | |
Ah | UCCLA1READDR | Uncorrectable CLA1 Read Error Address | Go | |
20h | CERRFLG | Correctable Error Flag Register | Go | |
22h | CERRSET | Correctable Error Flag Set Register | EALLOW | Go |
24h | CERRCLR | Correctable Error Flag Clear Register | EALLOW | Go |
26h | CCPUREADDR | Correctable CPU Read Error Address | Go | |
2Eh | CERRCNT | Correctable Error Count Register | Go | |
30h | CERRTHRES | Correctable Error Threshold Value Register | EALLOW | Go |
32h | CEINTFLG | Correctable Error Interrupt Flag Status Register | Go | |
34h | CEINTCLR | Correctable Error Interrupt Flag Clear Register | EALLOW | Go |
36h | CEINTSET | Correctable Error Interrupt Flag Set Register | EALLOW | Go |
38h | CEINTEN | Correctable Error Interrupt Enable Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-319 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
UCERRFLG is shown in Figure 3-286 and described in Table 3-320.
Return to the Summary Table.
Uncorrectable Error Flag Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1RDERR | DMARDERR | CPURDERR | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | CLA1RDERR | R | 0h | CLA1 Uncorrectable Read Error Flag 0: No Error. 1: Uncorrectable error occurred during CLA1 read. Reset type: SYSRSn |
1 | DMARDERR | R | 0h | DMA Uncorrectable Read Error Flag 0: No Error. 1: Uncorrectable error occurred during DMA read. Reset type: SYSRSn |
0 | CPURDERR | R | 0h | CPU Uncorrectable Read Error Flag 0: No Error. 1: Uncorrectable error occurred during CPU read. Reset type: SYSRSn |
UCERRSET is shown in Figure 3-287 and described in Table 3-321.
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Uncorrectable Error Flag Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1RDERR | DMARDERR | CPURDERR | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | CLA1RDERR | R-0/W1S | 0h | 0: No action. 1: CLA1 Read Error Flag in UCERRFLG register will be set and interrupt will be generated if enabled.. Reset type: SYSRSn |
1 | DMARDERR | R-0/W1S | 0h | 0: No action. 1: DMA Read Error Flag in UCERRFLG register will be set and interrupt will be generated if enabled.. Reset type: SYSRSn |
0 | CPURDERR | R-0/W1S | 0h | 0: No action. 1: CPU Read Error Flag in UCERRFLG register will be set and interrupt will be generated if enabled.. Reset type: SYSRSn |
UCERRCLR is shown in Figure 3-288 and described in Table 3-322.
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Uncorrectable Error Flag Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1RDERR | DMARDERR | CPURDERR | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | CLA1RDERR | R-0/W1S | 0h | 0: No action. 1: CLA1 Read Error Flag in UCERRFLG register will be cleared. Reset type: SYSRSn |
1 | DMARDERR | R-0/W1S | 0h | 0: No action. 1: DMA Read Error Flag in UCERRFLG register will be cleared . Reset type: SYSRSn |
0 | CPURDERR | R-0/W1S | 0h | 0: No action. 1: CPU Read Error Flag in UCERRFLG register will be cleared. Reset type: SYSRSn |
UCCPUREADDR is shown in Figure 3-289 and described in Table 3-323.
Return to the Summary Table.
Uncorrectable CPU Read Error Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCCPUREADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UCCPUREADDR | R | 0h | This register captures the address location for which CPU read/fetch access resulted in uncorrectable ECC/Parity error. Reset type: SYSRSn |
UCDMAREADDR is shown in Figure 3-290 and described in Table 3-324.
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Uncorrectable DMA Read Error Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCDMAREADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UCDMAREADDR | R | 0h | This register captures the address location for which DMA read access resulted in uncorrectable Parity error. Reset type: SYSRSn |
UCCLA1READDR is shown in Figure 3-291 and described in Table 3-325.
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Uncorrectable CLA1 Read Error Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UCCLA1READDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | UCCLA1READDR | R | 0h | This register captures the address location for which CLA1 read/fetch access resulted in uncorrectable Parity error. Reset type: SYSRSn |
CERRFLG is shown in Figure 3-292 and described in Table 3-326.
Return to the Summary Table.
Correctable Error Flag Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1RDERR | DMARDERR | CPURDERR | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | CLA1RDERR | R | 0h | CLA1 Correctable Read Error Flag 0: No Error. 1: Correctable error occurred during CLA1 read. Reset type: SYSRSn |
1 | DMARDERR | R | 0h | DMA Correctable Read Error Flag 0: No Error. 1: Correctable error occurred during DMA read. Reset type: SYSRSn |
0 | CPURDERR | R | 0h | CPU Correctable Read Error Flag 0: No Error. 1: Correctable error occurred during CPU read. Reset type: SYSRSn |
CERRSET is shown in Figure 3-293 and described in Table 3-327.
Return to the Summary Table.
Correctable Error Flag Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1RDERR | DMARDERR | CPURDERR | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | CLA1RDERR | R-0/W1S | 0h | 0: No action. 1: CLA1 Read Error Flag in CERRFLG register will be set and interrupt will be generated if enabled.. Reset type: SYSRSn |
1 | DMARDERR | R-0/W1S | 0h | 0: No action. 1: DMA Read Error Flag in CERRFLG register will be set and interrupt will be generated if enabled.. Reset type: SYSRSn |
0 | CPURDERR | R-0/W1S | 0h | 0: No action. 1: CPU Read Error Flag in CERRFLG register will be set and interrupt will be generated if enabled.. Reset type: SYSRSn |
CERRCLR is shown in Figure 3-294 and described in Table 3-328.
Return to the Summary Table.
Correctable Error Flag Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | CLA1RDERR | DMARDERR | CPURDERR | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | CLA1RDERR | R-0/W1S | 0h | 0: No action. 1: CLA1 Read Error Flag in CERRFLG register will be cleared. Reset type: SYSRSn |
1 | DMARDERR | R-0/W1S | 0h | 0: No action. 1: DMA Read Error Flag in CERRFLG register will be cleared . Reset type: SYSRSn |
0 | CPURDERR | R-0/W1S | 0h | 0: No action. 1: CPU Read Error Flag in CERRFLG register will be cleared. Reset type: SYSRSn |
CCPUREADDR is shown in Figure 3-295 and described in Table 3-329.
Return to the Summary Table.
Correctable CPU Read Error Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCPUREADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CCPUREADDR | R | 0h | This register captures the address location for which CPU read/fetch access resulted in correctable ECC error. Reset type: SYSRSn |
CERRCNT is shown in Figure 3-296 and described in Table 3-330.
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Correctable Error Count Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CERRCNT | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CERRCNT | R | 0h | This register holds the count of how many times correctable error occurred. Reset type: SYSRSn |
CERRTHRES is shown in Figure 3-297 and described in Table 3-331.
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Correctable Error Threshold Value Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CERRTHRES | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CERRTHRES | R/W | 0h | When value in CERRCNT register is greater than value configured in this register, corretable interrupt gets generated, if enabled. Reset type: SYSRSn |
CEINTFLG is shown in Figure 3-298 and described in Table 3-332.
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Correctable Error Interrupt Flag Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CEINTFLAG | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | CEINTFLAG | R | 0h | Total corrected error count exceeded threshold Flag 0: Total correctable errors < Threshold value configured in CERRTHRES register. 1: Total correctable errors >= Threshold value configured in CERRTHRES register. Reset type: SYSRSn |
CEINTCLR is shown in Figure 3-299 and described in Table 3-333.
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Correctable Error Interrupt Flag Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CEINTCLR | ||||||
R-0h | R-0/W1S-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | CEINTCLR | R-0/W1S | 0h | 0: No action. 1: Total corrected error count exceeded flag in CEINTFLG register will be cleared. Reset type: SYSRSn |
CEINTSET is shown in Figure 3-300 and described in Table 3-334.
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Correctable Error Interrupt Flag Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CEINTSET | ||||||
R-0h | R-0/W1S-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | CEINTSET | R-0/W1S | 0h | 0: No action. 1: Total corrected error count exceeded flag in CEINTFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
CEINTEN is shown in Figure 3-301 and described in Table 3-335.
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Correctable Error Interrupt Enable Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CEINTEN | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-1 | RESERVED | R | 0h | Reserved |
0 | CEINTEN | R/W | 0h | 0: Correctable Error Interrupt is disabled. 1: Correctable Error Interrupt is enabled. Reset type: SYSRSn |