SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 11-3 lists the memory-mapped registers for the ERAD_GLOBAL_REGS registers. All register offset addresses not listed in Table 11-3 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | GLBL_EVENT_STAT | Global Event Status Register | Go | |
2h | GLBL_HALT_STAT | Global Halt Status Register | Go | |
4h | GLBL_ENABLE | Global Enable Register | EALLOW | Go |
6h | GLBL_CTM_RESET | Global Counter Reset | EALLOW | Go |
Ah | GLBL_OWNER | Global Ownership | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 11-4 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
GLBL_EVENT_STAT is shown in Figure 11-3 and described in Table 11-5.
Return to the Summary Table.
This register contains one bit for each of the bus comparator modules and the counter modules that are present in a device. Each bit directly reflects the state of the EVENT_FIRED bit of the corresponding module. This facilitates software to just read one register and find out if any of the debug modules had fired.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CTM4 | CTM3 | CTM2 | CTM1 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HWBP8 | HWBP7 | HWBP6 | HWBP5 | HWBP4 | HWBP3 | HWBP2 | HWBP1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11 | CTM4 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Counter unit 4. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
10 | CTM3 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Counter unit 3. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
9 | CTM2 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Counter unit 2. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
8 | CTM1 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Counter unit 1. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
7 | HWBP8 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Enhanced Bus Comparator (EBC) unit 8. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
6 | HWBP7 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Enhanced Bus Comparator (EBC) unit 7. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
5 | HWBP6 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Enhanced Bus Comparator (EBC) unit 6. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
4 | HWBP5 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Enhanced Bus Comparator (EBC) unit 5. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
3 | HWBP4 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Enhanced Bus Comparator (EBC) unit 4. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
2 | HWBP3 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Enhanced Bus Comparator (EBC) unit 3. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
1 | HWBP2 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Enhanced Bus Comparator (EBC) unit 2. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
0 | HWBP1 | R | 0h | This bit directly reflects the state of the EVENT_FIRED bit of the Enhanced Bus Comparator (EBC) unit 1. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
GLBL_HALT_STAT is shown in Figure 11-4 and described in Table 11-6.
Return to the Summary Table.
This register contains one bit for each of the bus comparator modules and the counter modules that are present in a device. Each bit directly reflects the state of the EVENT_FIRED status bit. This facilitates software to just read one register and find out if any of the debug modules have fired.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CTM4 | CTM3 | CTM2 | CTM1 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HWBP8 | HWBP7 | HWBP6 | HWBP5 | HWBP4 | HWBP3 | HWBP2 | HWBP1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11 | CTM4 | R | 0h | This bit directly reflects the state of the completed bit of the Counter unit 4. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
10 | CTM3 | R | 0h | This bit directly reflects the state of the completed bit of the Counter unit 3. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
9 | CTM2 | R | 0h | This bit directly reflects the state of the completed bit of the Counter unit 2. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
8 | CTM1 | R | 0h | This bit directly reflects the state of the completed bit of the Counter unit 1. 0 No Event 1 Event Fired Reset type: ERAD_RESET |
7 | HWBP8 | R | 0h | This bit directly reflects the state of the completed bit of the Enhanced Bus Comparator (EBC) unit 8. 0 Not Completed 1 Completed Reset type: ERAD_RESET |
6 | HWBP7 | R | 0h | This bit directly reflects the state of the completed bit of the Enhanced Bus Comparator (EBC) unit 7. 0 Not Completed 1 Completed Reset type: ERAD_RESET |
5 | HWBP6 | R | 0h | This bit directly reflects the state of the completed bit of the Enhanced Bus Comparator (EBC) unit 6. 0 Not Completed 1 Completed Reset type: ERAD_RESET |
4 | HWBP5 | R | 0h | This bit directly reflects the state of the completed bit of the Enhanced Bus Comparator (EBC) unit 5. 0 Not Completed 1 Completed Reset type: ERAD_RESET |
3 | HWBP4 | R | 0h | This bit directly reflects the state of the completed bit of the Enhanced Bus Comparator (EBC) unit 4. 0 Not Completed 1 Completed Reset type: ERAD_RESET |
2 | HWBP3 | R | 0h | This bit directly reflects the state of the completed bit of the Enhanced Bus Comparator (EBC) unit 3. 0 Not Completed 1 Completed Reset type: ERAD_RESET |
1 | HWBP2 | R | 0h | This bit directly reflects the state of the completed bit of the Enhanced Bus Comparator (EBC) unit 2. 0 Not Completed 1 Completed Reset type: ERAD_RESET |
0 | HWBP1 | R | 0h | This bit directly reflects the state of the completed bit of the Enhanced Bus Comparator (EBC) unit 1. 0 Not Completed 1 Completed Reset type: ERAD_RESET |
GLBL_ENABLE is shown in Figure 11-5 and described in Table 11-7.
Return to the Summary Table.
This register contains one bit for each of the bus comparator modules and the counter modules that are present in a device. Each bit directly acts as a global enable for the corresponding module. This bit has to be set to 1 for the module to be functional.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CTM4 | CTM3 | CTM2 | CTM1 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HWBP8 | HWBP7 | HWBP6 | HWBP5 | HWBP4 | HWBP3 | HWBP2 | HWBP1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R | 0h | Reserved |
11 | CTM4 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Counter unit 4. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
10 | CTM3 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Counter unit 3. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
9 | CTM2 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Counter unit 2. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
8 | CTM1 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Counter unit 1. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
7 | HWBP8 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Enhanced Bus Comparator (EBC) unit 8. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
6 | HWBP7 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Enhanced Bus Comparator (EBC) unit 7. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
5 | HWBP6 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Enhanced Bus Comparator (EBC) unit 6. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
4 | HWBP5 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Enhanced Bus Comparator (EBC) unit 5. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
3 | HWBP4 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Enhanced Bus Comparator (EBC) unit 4. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
2 | HWBP3 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Enhanced Bus Comparator (EBC) unit 3. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
1 | HWBP2 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Enhanced Bus Comparator (EBC) unit 2. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
0 | HWBP1 | R/W | 0h | This bit directly reflects the state of the ENABLE bit of the Enhanced Bus Comparator (EBC) unit 1. 0 Disabled 1 Enabled Reset type: ERAD_RESET |
GLBL_CTM_RESET is shown in Figure 11-6 and described in Table 11-8.
Return to the Summary Table.
This register contains one bit for each of the counter modules that are present in a device. Each bit directly acts as a reset for the counters for the corresponding module.(It does not affect anything else except resetting the counter.
Example: If the counter was previously incrementing before reset, then on a reset event the counter gets reset and continues to increment again).
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTM4 | CTM3 | CTM2 | CTM1 | |||
R-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | R-0/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-4 | RESERVED | R | 0h | Reserved |
3 | CTM4 | R-0/W | 0h | This bit directly resets the state the Counter unit 4. 0 No Effect 1 Reset Reset type: ERAD_RESET |
2 | CTM3 | R-0/W | 0h | This bit directly resets the state the Counter unit 3. 0 No Effect 1 Reset Reset type: ERAD_RESET |
1 | CTM2 | R-0/W | 0h | This bit directly resets the state the Counter unit 2. 0 No Effect 1 Reset Reset type: ERAD_RESET |
0 | CTM1 | R-0/W | 0h | This bit directly resets the state the Counter unit 1. 0 No Effect 1 Reset Reset type: ERAD_RESET |
GLBL_OWNER is shown in Figure 11-7 and described in Table 11-9.
Return to the Summary Table.
Global Ownership
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OWNER | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-2 | RESERVED | R | 0h | Reserved |
1-0 | OWNER | R/W | 0h | This register determines whether Application Code or Debugger owns this module or it's kept in No Owner state where debugger or application can access the module. 00 No Owner 01 Application owned 10 Debugger owned 11 Reserved Reset type: ERAD_RESET |