SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 7-2 lists the memory-mapped registers for the CLA_PROM_CRC32_REGS registers. All register offset addresses not listed in Table 7-2 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CRC32_CONTROLREG | CRC32-Control Register | EALLOW | Go |
2h | CRC32_STARTADDRESS | CRC32-Start address register | EALLOW | Go |
4h | CRC32_SEED | CRC32-Seed Register | EALLOW | Go |
6h | CRC32_STATUSREG | CRC32-Status Register | Go | |
8h | CRC32_CRCRESULT | CRC32-CRC result Register | Go | |
Ah | CRC32_GOLDENCRC | CRC32-Golden CRC register | Go | |
18h | CRC32_INTEN | CRC32-Interrupt enable register | EALLOW | Go |
1Ah | CRC32_FLG | CRC32-Interrupt Flag Register | Go | |
1Ch | CRC32_CLR | CRC32-Interrupt Clear Register | Go | |
1Eh | CRC32_FRC | CRC32-Interrupt Force Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-3 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value |
CRC32_CONTROLREG is shown in Figure 7-2 and described in Table 7-4.
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CRC32-Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | BLOCKSIZE | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HALT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FREE_SOFT | RESERVED | START | ||||
R-0-0h | R/W-0h | R-0-0h | R-0/W1S-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R-0 | 0h | Reserved |
22-16 | BLOCKSIZE | R/W | 0h | Block size: 0x0 : 1 KB (default) 0x1 : 2 KB 0x2 : 3 KB ... 0x7F : 128KB Note : If the value written to this register is greater than size of ROM then it is internally set to max allowed block size Reset type: CPU1.SYSRSn |
15-9 | RESERVED | R-0 | 0h | Reserved |
8 | HALT | R/W | 0h | Halt Bit : 0 : CRC calaculation will resume from where is has hanlted 1 : CRC calculation will be halted Notes: This bit has effect only after CRC calc is triggered by writing to START Bit Reset type: CPU1.SYSRSn |
7-5 | RESERVED | R-0 | 0h | Reserved |
4 | FREE_SOFT | R/W | 0h | emulation control bit : This bit controls behaviour of CRC calculation during emulations 0 : Soft, CRC module stops on MCLA dedug suspend. 1 : Free, CRC calucation is not affected by DEBUG HALT of CLA Reset type: CPU1.SYSRSn |
3-1 | RESERVED | R-0 | 0h | Reserved |
0 | START | R-0/W1S | 0h | Start Bit: 0: No effect 1: will start the CRC calulations Notes: Setting this anytime during the CRC caluclation will reset and re-start the CRC calulation. Reset type: CPU1.SYSRSn |
CRC32_STARTADDRESS is shown in Figure 7-3 and described in Table 7-5.
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CRC32-Start address register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START_ADDRESS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | START_ADDRESS | R/W | 0h | START_ADDRESS defines starting point for CRC32 calculation. Note that it is CLA address Reset type: CPU1.SYSRSn |
CRC32_SEED is shown in Figure 7-4 and described in Table 7-6.
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CRC32-Seed Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEED | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SEED | R/W | 0h | Initial value of CRC, this value is coiped to the CRC register on triggering CRC calculation by writing to START bit. Reset type: CPU1.SYSRSn |
CRC32_STATUSREG is shown in Figure 7-5 and described in Table 7-7.
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CRC32-Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RUNSTATUS | RESERVED | ||||||
R-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CRCCHECKSTATUS | RESERVED | ||||||
R-0h | R-0-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CURRENTADDR | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CURRENTADDR | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RUNSTATUS | R | 0h | Status bit: 0 : CRC module is IDLE 1 : CRC module is Active Reset type: CPU1.SYSRSn |
30-24 | RESERVED | R-0 | 0h | Reserved |
23 | CRCCHECKSTATUS | R | 0h | CRC pass/fail status bit: 0 : PASS 1 : FAIL Note: Comparion is enabled only after CRC calc is completed Reset type: CPU1.SYSRSn |
22-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | CURRENTADDR | R | 0h | The current address of data fetch unit - this is 32 bit aligned offset address of ROM Reset type: CPU1.SYSRSn |
CRC32_CRCRESULT is shown in Figure 7-6 and described in Table 7-8.
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CRC32-CRC result Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRCRESULT | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRCRESULT | R | 0h | CRC result register Reset type: CPU1.SYSRSn |
CRC32_GOLDENCRC is shown in Figure 7-7 and described in Table 7-9.
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CRC32-Golden CRC register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GOLDENCRC | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | GOLDENCRC | R/W | 0h | Golden CRC register: Value written to this register is compared with CRCRESULT when CRCDONE bit is set. After the CRC is done, GOLDENCRC will be compared with CRCRESULT and the CRCCHECKSTATUS bit will be updated. Reset type: CPU1.SYSRSn |
CRC32_INTEN is shown in Figure 7-8 and described in Table 7-10.
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CRC32-Interrupt enable register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRCDONE | RESERVED | |||||
R-0-0h | R/W-0h | R-0-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | CRCDONE | R/W | 0h | 0 CRCDONE Interrupt disabled 1 CRCDONE Interrupt enabled Reset type: CPU1.SYSRSn |
0 | RESERVED | R-0 | 0h | Reserved |
CRC32_FLG is shown in Figure 7-9 and described in Table 7-11.
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CRC32-Interrupt Flag Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRCDONE | INT | |||||
R-0-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | CRCDONE | R | 0h | Error Interrupt Status flag 0 CRC calulation is in progress or CRC module is idle. 1 CRC calulation is done. Reset type: CPU1.SYSRSn |
0 | INT | R | 0h | Global Interrupt Status flag 0 No interrupt generated 1 Interrupt was generated Reset type: CPU1.SYSRSn |
CRC32_CLR is shown in Figure 7-10 and described in Table 7-12.
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CRC32-Interrupt Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRCDONE | INT | |||||
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | CRCDONE | R-0/W1S | 0h | Clear CRCDONE interrupt flag 0 No effect 1 Clears the CRCDONE interrupt flag Reset type: CPU1.SYSRSn |
0 | INT | R-0/W1S | 0h | Global Interrupt Clear 0 No effect 1 Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1. Reset type: CPU1.SYSRSn |
CRC32_FRC is shown in Figure 7-11 and described in Table 7-13.
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CRC32-Interrupt Force Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRCDONE | RESERVED | |||||
R-0-0h | R-0/W1S-0h | R-0-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | CRCDONE | R-0/W1S | 0h | Force CRCDONE interrupt flag 0 No effect 1 Force CRCDONE interrupt flag Reset type: CPU1.SYSRSn |
0 | RESERVED | R-0 | 0h | Reserved |