SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 6-2 lists the memory-mapped registers for the DCC_REGS registers. All register offset addresses not listed in Table 6-2 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | DCCGCTRL | Global Control Register | Go | |
4h | DCCREV | DCC Revision Register | Go | |
8h | DCCCNTSEED0 | Counter 0 Seed Value | Go | |
Ch | DCCVALIDSEED0 | Valid 0 Seed Value | Go | |
10h | DCCCNTSEED1 | Counter 1 Seed Value | Go | |
14h | DCCSTATUS | DCC Status | Go | |
18h | DCCCNT0 | Counter 0 Value | Go | |
1Ch | DCCVALID0 | Valid Value 0 | Go | |
20h | DCCCNT1 | Counter 1 Value | Go | |
24h | DCCCLKSRC1 | Clock Source 1 | Go | |
28h | DCCCLKSRC0 | Clock Source 0 | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-3 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
R-1 | R -1 | Read Returns 1s |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
DCCGCTRL is shown in Figure 6-3 and described in Table 6-4.
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Starts / stops the counters. Clears the error signal.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DONEENA | SINGLESHOT | ERRENA | DCCENA | ||||||||||||
R/W-5h | R/W-5h | R/W-5h | R/W-5h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | 0h | Reserved |
15-12 | DONEENA | R/W | 5h | DONE Enable Enables/disables the done interrupt signal, but has no effect on the done status flag in DCCSTAT register. 0101 The done signal is disabled Others The done signal is enabled Reset type: SYSRSn |
11-8 | SINGLESHOT | R/W | 5h | Single-Shot Enable Enables/disables repetitive operation of the DCC. 1010 Stop counting when COUNTER0 and VALID0 both reach zero Note: Configure this to 0xA before Enabling DCC Note: All values other than 1010 are reserved Reset type: SYSRSn |
7-4 | ERRENA | R/W | 5h | Error Enable Enables/disables the error signal. 0101 The error signal is disabled Others The error signal is enabled Reset type: SYSRSn |
3-0 | DCCENA | R/W | 5h | DCC Enable Starts and stops the operation of the DCC. 0101 Counters are stopped Others Counters are running Reset type: SYSRSn |
DCCREV is shown in Figure 6-4 and described in Table 6-5.
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Specifies the module version.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | |||||
R-1-1h | R-0-0h | R-4h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-4h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAJOR | ||||||
R-2h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MINOR | ||||||
R-0h | R-3h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R-1 | 1h | Reserved |
29-28 | RESERVED | R-0 | 0h | Reserved |
27-16 | RESERVED | R | 4h | Reserved |
15-11 | RESERVED | R | 2h | Reserved |
10-8 | MAJOR | R | 0h | Major Revision Number Represents major changes to the module (e.g. entirely new features are added/changed). The major revision number for this module. Reset type: SYSRSn |
7-6 | RESERVED | R | 0h | Reserved |
5-0 | MINOR | R | 3h | Minor Revision Number Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. Reset type: SYSRSn |
DCCCNTSEED0 is shown in Figure 6-5 and described in Table 6-6.
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Seed value for the counter attached to Clock Source 0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNTSEED0 | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-0 | COUNTSEED0 | R/W | 0h | Seed Value for Counter 0 Contains the seed value that gets loaded into Counter 0 (Clock Source 0). NOTE: Operating the DCC with '0' in the COUNTSEED0 register will result in undefined operation. Reset type: SYSRSn |
DCCVALIDSEED0 is shown in Figure 6-6 and described in Table 6-7.
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Seed value for the timeout counter attached to Clock Source 0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALIDSEED | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VALIDSEED | R/W | 0h | Seed Value for Valid Duration Counter 0 Contains the seed value that gets loaded into the valid duration counter for Clock Source 0. NOTE: Operating the DCC with '0' in the VALIDSEED0 register will result in undefined operation. VALID0 defines a window in which COUNT1 expires. This window is meant to be at least four cycles wide. Do not program a value less than '4' into the VALID0 register. Reset type: SYSRSn |
DCCCNTSEED1 is shown in Figure 6-7 and described in Table 6-8.
Return to the Summary Table.
Seed value for the counter attached to Clock Source 1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNTSEED1 | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-0 | COUNTSEED1 | R/W | 0h | Seed Value for Counter 1 Contains the seed value that gets loaded into Counter 1 (Clock Source 1). NOTE: Operating the DCC with '0' in the COUNTSEED1 register will result in undefined operation. Reset type: SYSRSn |
DCCSTATUS is shown in Figure 6-8 and described in Table 6-9.
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Specifies the status of the DCC Module.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DONE | ERR | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | DONE | R/W | 0h | Single-Shot Done Flag Indicates when single-shot mode is complete without error. Writing a '1' to this bit clears the flag. 0 Single-shot mode has not completed. 1 Single-shot mode has completed. Reset type: SYSRSn |
0 | ERR | R/W | 0h | Error Flag Indicates whether or not an error has occurred. Writing a '1' to this bit clears the flag. 0 No errors have occurred. 1 An error has occurred. Reset type: SYSRSn |
DCCCNT0 is shown in Figure 6-9 and described in Table 6-10.
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Value of the counter attached to Clock Source 0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT0 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-0 | COUNT0 | R | 0h | Current Value of Counter 0 Reset type: SYSRSn |
DCCVALID0 is shown in Figure 6-10 and described in Table 6-11.
Return to the Summary Table.
Value of the valid counter attached to Clock Source 0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALID0 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VALID0 | R | 0h | Current Value of Valid 0 Reset type: SYSRSn |
DCCCNT1 is shown in Figure 6-11 and described in Table 6-12.
Return to the Summary Table.
Value of the counter attached to Clock Source 1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT1 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-0 | COUNT1 | R | 0h | Current Value of Counter 1 Reset type: SYSRSn |
DCCCLKSRC1 is shown in Figure 6-12 and described in Table 6-13.
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Selects the clock source for Counter 1.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | RESERVED | CLKSRC1 | |||||||||||||
R-0/W-5h | R-0h | R/W-2h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | KEY | R-0/W | 5h | Enables or Disables Clock Source Write for COUNT1 1010: The CLKSRC1 field written with key gets updated to with new selection to clock COUNT1. Others: Previous values retained new writes on register fields has no impact. Reset type: SYSRSn |
11-4 | RESERVED | R | 0h | Reserved |
3-0 | CLKSRC1 | R/W | 2h | Clock Source Select for Counter 1 Specifies the clock source for COUNT1, when the KEY field enables this feature. Note: Any values not explicitly defined below are reserved. Reset type: SYSRSn 0h (R/W) = Direct output of SYSPLL CLKOUT 1h (R/W) = Reserved 2h (R/W) = INTOSC1 output clock 3h (R/W) = INTOSC2 output clock 4h (R/W) = Reserved 5h (R/W) = Reserved 6h (R/W) = System clock 7h (R/W) = Reserved 8h (R/W) = Reserved 9h (R/W) = Input 15 of INPUTXBAR1 Ah (R/W) = Auxiliary clock input Bh (R/W) = Clock input to EPWM module Ch (R/W) = Bit clock for SPI and SCI modules Dh (R/W) = ADC conversion clock Eh (R/W) = Watchdog clock after dividers Fh (R/W) = CAN0 bit clock |
DCCCLKSRC0 is shown in Figure 6-13 and described in Table 6-14.
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Selects the clock source for Counter 0.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKSRC0 | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | CLKSRC0 | R/W | 1h | Clock Source Select for Counter 0 Specifies the clock source for COUNT0, when the KEY field enables this feature. Note: All values not defined below are reserved. Reset type: SYSRSn 0h (R/W) = Crystal oscillator output 1h (R/W) = INTOSC1 output 2h (R/W) = INTOSC2 output |