SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
Table 10-452 lists the memory-mapped registers for the DMA_CLA_SRC_SEL_REGS registers. All register offset addresses not listed in Table 10-452 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CLA1TASKSRCSELLOCK | CLA1 Task Trigger Source Select Lock Register | EALLOW | Go |
4h | DMACHSRCSELLOCK | DMA Channel Triger Source Select Lock Register | EALLOW | Go |
6h | CLA1TASKSRCSEL1 | CLA1 Task Trigger Source Select Register-1 | EALLOW | Go |
8h | CLA1TASKSRCSEL2 | CLA1 Task Trigger Source Select Register-2 | EALLOW | Go |
16h | DMACHSRCSEL1 | DMA Channel Trigger Source Select Register-1 | EALLOW | Go |
18h | DMACHSRCSEL2 | DMA Channel Trigger Source Select Register-2 | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 10-453 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CLA1TASKSRCSELLOCK is shown in Figure 10-395 and described in Table 10-454.
Return to the Summary Table.
CLA1 Task Trigger Source Select Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLA1TASKSRCSEL2 | CLA1TASKSRCSEL1 | |||||
R-0-0h | R/WSonce-0h | R/WSonce-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | CLA1TASKSRCSEL2 | R/WSonce | 0h | CLA1TASKSRCSEL2 Register Lock bit: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any SOnce bit in this register, once set can only be cleared through a SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: SYSRSn |
0 | CLA1TASKSRCSEL1 | R/WSonce | 0h | CLA1TASKSRCSEL1 Register Lock bit: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any SOnce bit in this register, once set can only be cleared through a SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: SYSRSn |
DMACHSRCSELLOCK is shown in Figure 10-396 and described in Table 10-455.
Return to the Summary Table.
DMA Channel Triger Source Select Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMACHSRCSEL2 | DMACHSRCSEL1 | |||||
R-0-0h | R/WSonce-0h | R/WSonce-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | DMACHSRCSEL2 | R/WSonce | 0h | DMACHSRCSEL2 Register Lock bit: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any SOnce bit in this register, once set can only be cleared through a SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: SYSRSn |
0 | DMACHSRCSEL1 | R/WSonce | 0h | DMACHSRCSEL1 Register Lock bit: 0: Respective register is not locked 1: Respective register is locked. Notes: [1] Any SOnce bit in this register, once set can only be cleared through a SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed Reset type: SYSRSn |
CLA1TASKSRCSEL1 is shown in Figure 10-397 and described in Table 10-456.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TASK4 | TASK3 | TASK2 | TASK1 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | TASK4 | R/W | 0h | Selects the Trigger Source for TASK4 of CLA1 Reset type: SYSRSn |
23-16 | TASK3 | R/W | 0h | Selects the Trigger Source for TASK3 of CLA1 Reset type: SYSRSn |
15-8 | TASK2 | R/W | 0h | Selects the Trigger Source for TASK2 of CLA1 Reset type: SYSRSn |
7-0 | TASK1 | R/W | 0h | Selects the Trigger Source for TASK1 of CLA1 Reset type: SYSRSn |
CLA1TASKSRCSEL2 is shown in Figure 10-398 and described in Table 10-457.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TASK8 | TASK7 | TASK6 | TASK5 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | TASK8 | R/W | 0h | Selects the Trigger Source for TASK8 of CLA1 Reset type: SYSRSn |
23-16 | TASK7 | R/W | 0h | Selects the Trigger Source for TASK7 of CLA1 Reset type: SYSRSn |
15-8 | TASK6 | R/W | 0h | Selects the Trigger Source for TASK6 of CLA1 Reset type: SYSRSn |
7-0 | TASK5 | R/W | 0h | Selects the Trigger Source for TASK5 of CLA1 Reset type: SYSRSn |
DMACHSRCSEL1 is shown in Figure 10-399 and described in Table 10-458.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH4 | CH3 | CH2 | CH1 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | CH4 | R/W | 0h | Selects the Trigger and Sync Source CH4 of DMA Reset type: SYSRSn |
23-16 | CH3 | R/W | 0h | Selects the Trigger and Sync Source CH3 of DMA Reset type: SYSRSn |
15-8 | CH2 | R/W | 0h | Selects the Trigger and Sync Source CH2 of DMA Reset type: SYSRSn |
7-0 | CH1 | R/W | 0h | Selects the Trigger and Sync Source CH1 of DMA Reset type: SYSRSn |
DMACHSRCSEL2 is shown in Figure 10-400 and described in Table 10-459.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH6 | CH5 | |||||||||||||||||||||||||||||
R-0-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | CH6 | R/W | 0h | Selects the Trigger and Sync Source CH6 of DMA Reset type: SYSRSn |
7-0 | CH5 | R/W | 0h | Selects the Trigger and Sync Source CH5 of DMA Reset type: SYSRSn |