SPRUI33H November 2015 – June 2024 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
The missing clock detection (MCD) subsystem detects OSCCLK failure using INTOSC1 as a reference clock. This subsystem only detects complete loss of OSCCLK. Frequency drift is not detected.
OSCCLK is connected to a 7-bit counter (MCDPCNT). INTOSC1 is connected to a 13-bit counter (MCDSCNT). When MCDPCNT overflows, MCDSCNT is reset. Thus, if OSCCLK is present and the frequency is greater than 1/64 of the INTOSC1 frequency, MCDSCNT never overflows. If OSCCLK stops for any reason, MCDSCNT overflows and a missing clock condition is detected. Missing clock detection time is 8192 INTOSC1 cycles (819.2µs assuming INTOSC1 = 10MHz).
When the MCD subsystem detects that OSCCLK is missing, the following occurs:
To clear a missing clock condition, write a 1 to the MCDCR.MCLKCLR bit. This restores the functionality of the OSCCLKSRCSEL bits and resets the MCD counters. The user can also write to the PLL registers to re-lock the PLL. Under this situation, the missing clock detect circuit is automatically re-enabled (PLLSTS[MCLKSTS] bit is automatically cleared).
Missing clock detection in enabled at startup.