There are three classes of registers that are used
to control and configure the CLB tile. This specification only describes the offset
addresses of the registers. The absolute register addresses are different for each CLB tile.
The three instances of the various blocks (LUT4, FSM, and Counter Block) are numbered 0, 1,
and 2.
- Logic configuration registers (0x000 – 0x0FF): These registers control
the core reconfiguration logic for the tile. All registers in this group are EALLOW
protected and also protected by the LOCK register.
- Top level control registers (0x100 – 0x1FF): These registers are used
for top level and device related control of the CLB. These registers typically control mux
selects for inputs, global enables, and so forth, and are accessible by normal memory
mapped access. Some of these registers have EALLOW and LOCK protection.
- Data exchange registers (0x200 – 0x3FF): These registers are used to
exchange data between the CLB and the rest of the device. The registers are accessible by
normal memory-mapped access and no EALLOW or LOCK protection exists.
Note: EALLOW protection means that the write access
to the register is enabled only when the EALLOW instruction has been executed prior to the
write access. The complementary EDIS instruction disables access to all registers protected
in this way. For more information, see
Section 29.8.