SPRUI33 User guide

18.10.1 Operational Overview of the ePWM Event-Trigger Submodule

The event-trigger submodule monitors various event conditions (shown as inputs on the left side of Figure 18-45) and can be configured to prescale these events before issuing an Interrupt request or an ADC start of conversion. The event-trigger prescaling logic can issue Interrupt requests and ADC start of conversion at:

Every event
Every second event
Up to every fifteenth event

F28004x Event-Trigger
Submodule Showing Event Inputs and Prescaled Outputs

Figure 18-45 Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs

ETSEL - This selects which of the possible events trigger an interrupt or start an ADC conversion.
ETPS - This programs the event prescaling options mentioned above.
ETFLG - These are flag bits indicating status of the selected and prescaled events.
ETCLR - These bits allow clearing the flag bits in the ETFLG register using software.
ETFRC - These bits allow software forcing of an event. Useful for debugging or software intervention.
ETINTPS - This programs the interrupt event prescaling options, supporting count and period up to 15 events.
ETSOCPS - This programs the SOC event prescaling options, supporting count and period up to 15 events.
ETCNTINITCTL - These bits enable ETCNTINIT initialization using SYNC event or using software force.
ETCNTINIT - These bits allow initializing INT/SOCA/SOCB counters on SYNC events (or software force) with user programmed value.

A more detailed look at how the various register bits interact with the Interrupt and ADC start of conversion logic are shown in Figure 18-46, Figure 18-47, and Figure 18-48.

Figure 18-46 shows the event-trigger's interrupt generation logic. The interrupt-period (ETPS[INTPRD]) bits specify the number of events required to cause an interrupt pulse to be generated. The choices available are:

Do not generate an interrupt.
Generate an interrupt on every event.
Generate an interrupt on every second event.
Generate an interrupt on every third event.

The selection made on ETPS[INTPSSEL] bit determines whether ETINTPS register, INTCNT2 and INTPRD2 bit fields determine frequency of events (interrupt once every 0-15 events).

The event that can cause an interrupt is configured by the interrupt selection (ETSEL[INTSEL]) and (ETSEL[INTSELCMP]) bits. The event can be one of the following:

Time-base counter equal to zero (TBCTR = 0x00).
Time-base counter equal to period (TBCTR = TBPRD).
Time-base counter equal to zero or period (TBCTR = 0x00 || TBCTR = TBPRD).
Time-base counter equal to the compare A register (CMPA) when the timer is incrementing.
Time-base counter equal to the compare A register (CMPA) when the timer is decrementing.
Time-base counter equal to the compare B register (CMPB) when the timer is incrementing.
Time-base counter equal to the compare B register (CMPB) when the timer is decrementing.
Time-base counter equal to the compare C register (CMPC) when the timer is incrementing.
Time-base counter equal to the compare C register (CMPC) when the timer is decrementing.
Time-base counter equal to the compare D register (CMPD) when the timer is incrementing.
Time-base counter equal to the compare D register (CMPD) when the timer is decrementing.

The number of events that have occurred can be read from the interrupt event counter ETPS[INTCNT] or ETINTPS[INTCNT2] register bits based off of the selection made using ETPS[INTPSSEL]. That is, when the specified event occurs the ETPS[INTCNT] or ETINTPS[INTCNT2] bits are incremented until the bits reach the value specified by ETPS[INTPRD] or ETINTPS[INTPRD2] determined again by the selection made in ETPS[INTPSSEL]. When ETPS[INTCNT] = ETPS[INTPRD], the counter stops counting and the counter output is set. The counter is only cleared when an interrupt is sent to the interrupt controller.

When ETPS[INTCNT] reaches ETPS[INTPRD], the following behavior occurs. [The following behavior is also applicable to ETINTPS[INTCNT2] and ETINTPS[INTPRD2]:

If interrupts are enabled, ETSEL[INTEN] = 1 and the interrupt flag is clear, ETFLG[INT] = 0, then an interrupt pulse is generated and the interrupt flag is set, ETFLG[INT] = 1, and the event counter is cleared ETPS[INTCNT] = 0. The counter begins counting events again.
If interrupts are disabled, ETSEL[INTEN] = 0, or the interrupt flag is set, ETFLG[INT] = 1, the counter stops counting events when the counter reaches the period value ETPS[INTCNT] = ETPS[INTPRD].
If interrupts are enabled, but the interrupt flag is already set, then the counter holds the output high until the ENTFLG[INT] flag is cleared. This allows for one interrupt to be pending while one is serviced.

Writing a 0 to the INTPRD bits automatically clears the counter (INTCNT = 0) and the counter output resets (so no interrupts are generated). For all other writes to INTPRD, INTCNT retains the previous value. INTCNT resets when INTCNT overflows. Writing a 1 to the ETFRC[INT] bit increments the event counter INTCNT. The counter behaves as previously described when INTCNT = INTPRD. When INTPRD = 0, the counter is disabled and hence no events are detected and the ETFRC[INT] bit is also ignored. The same applies to ETINTPS[INTCNT2] and ETINTPS[INTPRD2].

The previous definition means that an interrupt on every event, on every second event, or on every third event if using the INTCNT and INTPRD can be generated. An interrupt on every event up to 15 events if using the INTCNT2 and INTPRD2 can be generated.

The INTCNT2 value can be initialized with the value from ETCNTINIT[INTINIT] based on the selection made in ETCNTINITCTL[INTINITEN]. When ETCNTINITCTL[INTINITEN] is set, then initialization of INTCNT2 counter with contents of ETCNTINIT[INTINIT] on a SYNC event or software force is determined by ETCNTINITCTL[INTINITFRC].

F28004x Event-Trigger Interrupt Generator

Figure 18-46 Event-Trigger Interrupt Generator

Figure 18-47 shows the operation of the event-trigger's start-of-conversion-A (SOCA) pulse generator. The enhancements include SOCASELCMP and SOCBSELCMP bit fields defined in the ETSEL register enable CMPC and CMPD events respectively to cause a start of conversion. The ETPS[SOCPSSEL] bit field determines whether SOCACNT2 and SOCAPRD2 take control or not. The ETPS[SOCACNT] counter and ETPS[SOCAPRD] period values behave similarly to the interrupt generator except that the pulses are continuously generated. That is, the pulse flag ETFLG[SOCA] is latched when a pulse is generated, but the interrupt generator does not stop further pulse generation. The enable and disable bit ETSEL[SOCAEN] stops pulse generation, but input events can still be counted until the period value is reached as with the interrupt generation logic. The event that triggers an SOCA and SOCB pulse can be configured separately in the ETSEL[SOCASEL] and ETSEL[SOCBSEL] bits. The possible events are the same events that can be specified for the interrupt generation logic with the addition of the DCAEVT1.soc and DCBEVT1.soc event signals from the digital compare (DC) submodule. The SOCACNT2 initialization scheme is very similar to the interrupt generator with respective enable, value initialize and SYNC or software force options.

F28004x Event-Trigger SOCA Pulse Generator

NOTE: The DCAEVT1.soc signals are generated by the Digital Compare (DC) submodule in Section 18.11.

Figure 18-47 Event-Trigger SOCA Pulse Generator

Figure 18-48 shows the operation of the event-trigger's start-of-conversion-B (SOCB) pulse generator. The event-trigger's SOCB pulse generator operates the same way as the SOCA.

F28004x Event-Trigger SOCB Pulse Generator

NOTE: The DCBEVT1.soc signals are generated by the Digital Compare (DC) submodule in Section 18.11.

Figure 18-48 Event-Trigger SOCB Pulse Generator