SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4A08 4C04 0x4A09 6804 | Instance | DPLLCTRL_USB_OTG_SS DPLLCTRL_SATA |
Description | This register contains the status information | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_TICOPWDN | PLL_LDOPWDN | RESERVED | SSC_EN_ACK | RESERVED | PLL_HIGHJITTER | RESERVED | PLL_LOSSREF | PLL_RECAL | PLL_LOCK | PLLCTRL_RESET_DONE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:17 | RESERVED | R | 0x0000 | |
16 | PLL_TICOPWDN | PLL TICOPWDN status. | R | 0 |
Read 0x1: Internal oscillator power down | ||||
Read 0x0: Internal oscillator power up | ||||
15 | PLL_LDOPWDN | PLL LDOPWDN status. | R | 0 |
Read 0x1: PLL's internal LDO is power down | ||||
Read 0x0: PLL's internal LDO is power up | ||||
14:13 | RESERVED | 0 | ||
12 | SSC_EN_ACK | Spread Spectrum Clocking acknowledge | R | 0 |
Read 0x1: Spread Spectrum Clocking active | ||||
Read 0x0: Spread Spectrum Clocking inactive | ||||
11:6 | RESERVED | R | 0x00 | |
5 | PLL_HIGHJITTER | PLL High Jitter status | R | 0 |
Read 0x1: PLL in high jitter condition: Phase error > 24% | ||||
Read 0x0: PLL in normal jitter condition | ||||
4 | RESERVED | Read returns zero. | R | 0 |
3 | PLL_LOSSREF | PLL Reference Loss status | R | 0 |
Read 0x1: Reference input inactive | ||||
Read 0x0: Reference input active | ||||
2 | PLL_RECAL | PLL re-calibration status If this bit is active, the PLL needs to be re-calibrated | R | 0 |
Read 0x1: Recalibration is required | ||||
Read 0x0: Recalibration is not required | ||||
1 | PLL_LOCK | PLL Lock status See the programming guide for the use of this bit | R | 0 |
Read 0x1: PLL is locked | ||||
Read 0x0: PLL is not locked | ||||
0 | PLLCTRL_RESET_DONE | PLLCTRL reset done status | R | 0 |
Read 0x1: Reset has completed | ||||
Read 0x0: Reset is in progress |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4A08 4C08 0x4A09 6808 | Instance | DPLLCTRL_USB_OTG_SS DPLLCTRL_SATA |
Description | This register contains the GO bit | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_GO |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | Reads return zero. | RW | 0x0000 0000 |
0 | PLL_GO | Request (re-)locking sequence of the PLL. | RW | 0 |
0x0: No pending action | ||||
0x1: Request PLL (re-)locking/locking pending |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4A08 4C0C 0x4A09 680C | Instance | DPLLCTRL_USB_OTG_SS DPLLCTRL_SATA |
Description | This register contains the latched PLL and HSDIVDER configuration bits | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_REGM | PLL_REGN | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:21 | RESERVED | RW | 0x000 | |
20:9 | PLL_REGM | M Divider for PLL | RW | 0x000 |
8:1 | PLL_REGN | N Divider for PLL (Reference) | RW | 0x00 |
0 | RESERVED | Read returns zero. | R | 0 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4A08 4C10 0x4A09 6810 | Instance | DPLLCTRL_USB_OTG_SS DPLLCTRL_SATA |
Description | This register contains the unlatched PLL and HSDIVDER configuration bits These bits are "shadowed" when automatic mode is selected | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_LOCKSEL | RESERVED | PLL_SELFREQDCO | PLL_IDLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:11 | RESERVED | RW | 0x00004 | |
10:9 | PLL_LOCKSEL | Selects the lock criteria for the PLL | RW | 0x0 |
0x0: Phase Lock | ||||
0x1: Frequency Lock | ||||
Other values: Reserved | ||||
8:4 | RESERVED | RW | 0x00 | |
3:1 | PLL_SELFREQDCO | DCO frequency range selector for DPLL_USB_OTG_SS / DPLLCTRL_SATA 0x2 Set if DCO frequency is between 750MHz and 1500MHz 0x4 Set if DCO frequency is between 1250MHz and 2500MHz Other values: Reserved | RW | 0x4 |
0 | PLL_IDLE | PLL IDLE: | RW | 0 |
0x0: IDLE is not selected | ||||
0x1: IDLE is selected |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4A08 4C14 0x4A09 6814 | Instance | DPLLCTRL_USB_OTG_SS DPLLCTRL_SATA |
Description | HSDIVIDER configuration bits for the M5 and M6 dividers | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_SD | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:18 | RESERVED | R | 0x0000 | |
17:10 | PLL_SD | Sigma delta divider setting for DPLL_USB_OTG_SS based on the PLL lock configuration. | RW | 0x00 |
9:0 | RESERVED | RW | 0x000 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4A08 4C18 0x4A09 6818 | Instance | DPLLCTRL_USB_OTG_SS DPLLCTRL_SATA |
Description | Configuration for PLL Spread Spectrum Clocking modulation | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DOWNSPREAD | RESERVED | EN_SSC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:3 | RESERVED | R | 0x0000 0000 | |
2 | DOWNSPREAD | Forces the clock spreading only in the down spectrum. | RW | 0 |
0x0: Clock spreading not forced. | ||||
0x1: Spectrum spreading only in down direction. | ||||
1 | RESERVED | RW | 0 | |
0 | EN_SSC | Spread Spectrum Clocking enable | RW | 0 |
0x0: Spread Spectrum Clocking disabled | ||||
0x1: Spread Spectrum Clocking enabled |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4A08 4C1C 0x4A09 681C | Instance | DPLLCTRL_USB_OTG_SS DPLLCTRL_SATA |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DELTAM2 | MODFREQDIVIDER | DELTAM |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | Reads as zero | R | 0 |
30 | DELTAM2 | MSB of DeltaM control bus. | RW | 0 |
29:20 | MODFREQDIVIDER | Modulation Frequency Divider control for SSC. | RW | 0x000 |
19:0 | DELTAM | DeltaM control for SSC. | RW | 0x0 0000 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4A08 4C20 0x4A09 6820 | Instance | DPLLCTRL_USB_OTG_SS DPLLCTRL_SATA |
Description | Allows setting the fractional M divider and M2 divider for PLL. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PLL_REGM_F |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:18 | RESERVED | Reads as 0x1 | RW | 0x0001 |
17:0 | PLL_REGM_F | Fractional part of M divider. | RW | 0x0 0000 |