SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | 0x0000 000C | ||
Physical Address | 0x4A09 440C 0x4A09 540C | Instance | PCIe1_PHY_TX PCIe2_PHY_TX |
Description | Functional Configuration registers | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_INVPAIR | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | MEM_INVPAIR | Invert polarity of TXP/TXN | RW | 0 |
30:0 | RESERVED | R | 0x0000 0000 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4A09 4410 0x4A09 5410 | Instance | PCIe1_PHY_TX PCIe2_PHY_TX |
Description | Configures the Driver data pattern | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_EVEN_OUT_CONFIG0 | MEM_ODD_OUT_CONFIG0 | MEM_EVEN_OUT_CONFIG1 | MEM_ODD_OUT_CONFIG1 | MEM_HS_RATE_ANA_OVERRIDE | MEM_OVRD_HS_RATE_ANA_OVERRIDE | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:25 | MEM_EVEN_OUT_CONFIG0 | Overriding the even TX data driver - to AFE | RW | 0x0 |
24:18 | MEM_ODD_OUT_CONFIG0 | Overriding the odd TX data driver - to AFE | RW | 0x0 |
17:11 | MEM_EVEN_OUT_CONFIG1 | Overriding the even TX data driver - to AFE | RW | 0x0 |
10:4 | MEM_ODD_OUT_CONFIG1 | Overriding the odd TX data driver - to AFE | RW | 0x0 |
3:2 | MEM_HS_RATE_ANA_OVERRIDE | Override for the HS rate signal going to the AFE | RW | 0x0 |
1 | MEM_OVRD_HS_RATE_ANA_OVERRIDE | Pin override for the hs_rate_ana_override | RW | 0x0 |
0 | RESERVED | Reserved | RW | 0x0 |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4A09 442C 0x4A09 542C | Instance | PCIe1_PHY_TX PCIe2_PHY_TX |
Description | Test related configuration registers | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MEM_EN_LPBK | MEM_ENTXPATT | MEM_TESTPATT | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | Keep at 0 | R | 0 |
30 | MEM_EN_LPBK | Loopback enable for test | RW | 0 |
29 | MEM_ENTXPATT | Enable Test pattern to input of the serializer instead of TD | RW | 0 |
28:26 | MEM_TESTPATT | Select the LFSR mode to generate the required pattern 000 - 31 bit LFSR mode 011 - 23 bit LFSR mode 010 - 7 bit LFSR mode 001 - generate 1010 pattern 100 - Fixed 31 bit value from pattgen_preload_val | RW | 0x0 |
25:0 | RESERVED | RW | 0x0 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4A09 4430 0x4A09 5430 | Instance | PCIe1_PHY_TX PCIe2_PHY_TX |
Description | Pattern generator (31 bit) LFSR Seed or preload value | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_PATTGEN_PRELOAD_VAL | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | MEM_PATTGEN_PRELOAD_VAL | Preload value to the LFSR pattern generator | RW | 0x0000 0000 |
0 | RESERVED | RW | 0 |