SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The USB3.0 physical layer (PHY) is responsible for transmitting the USB1 controller media access layer (MAC) 32-bit parallel data output as a serial data stream over a differential pair (TXP/TXN) and converting the differentially received serial data (RXP/RXN) to 32-bit parallel input data demanded by the MAC receiver logic.
The USB3_PHY component operates with a 2.5 GHz-source clock, to achieve the USB 3.0 super-speed throughput of 5 Gbps. The USB3_PHY serializer/deserializer source clock is generated by a DPLL clock generator (DPLL_USB_OTG_SS) which isintegrated into the USB1 host subsystem.
The DPLL_USB_OTG_SS is configured and controlled through the USB3_PHY dedicated PLL controller (DPLLCTRL_USB_OTG_SS) with associated serial configuration port (SCP) accessible registers.
A common interconnect adapter component, OCP2SCP1, lets the user program the USB3_PHY serializer/deserializer and DPLLCTRL_USB_OTG_SS through the L4_CFG interconnect.
Figure 28-8 gives an overview of the USB3_PHY subsystem. Figure 28-8 shows that the USB3_PHY serializer and deserializer directly interract with the attached to USB OTG SS controller USB3.0 compatible device (over TXP/TXN transmission and RXP/RXN reception interface I/Os). The PIPE port interracts with the USB1 MAC port, described in details in Section 26.7, SuperSpeed USB DRD.