SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The program cache controller supports a programmable invalidate mechanism, with which the starting address and the number of words to invalidate can be specified to start an invalidation sequence. The programming model for the invalidation mechanism consist of two memory mapped registers: the start address register (EVE_PC_IBAR[31:0] ADDR) that holds the start address and the byte count register (EVE_PC_IBC[15:0] BC) that holds the number of bytes to be invalidated.
The invalidate operation begins immediately with the writing into EVE_PC_IBC[15:0] BC (maximum = 0x8000). The application first sets the EVE_PC_IBAR[31:0] ADDR bit field and then the byte count register to ensure correct operation. The operation involves cycling through addresses starting from the value of EVE_PC_IBAR[31:0] ADDR in increments of the cache line size, doing tag lookups to check if the line exists in the cache. If the line exists in cache, the corresponding valid bit is reset. The. EVE_PC_IBC[15:0] BC bit field is reset to 0 when the invalidate completes. As the byte count register is readable, a check for 0 provides a synchronization event for the application to execute from the region being invalidated or before issuing another range-based invalidate.
EVE_PC_IBAR[31:0] ADDR can be any arbitrary byte address; whereas the invalidate operation occurs on cache-lines (that is, 32-bit aligned). Thus the range invalidated is effectively rounded down to the nearest cache-line address relative to the start address, and rounded up to include the entire cache line relative to the end address.
As in the global invalidate case, any CPU program fetches issued during the invalidate-range operation are stalled until the invalidation completes.