SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
To unmask an interrupt for generation of the SIMCOP_IRQi output interrupts, software must set the corresponding bit of the SIMCOP_HL_IRQENABLE_SET_i (I = 0 to 3) register to 1.
Example 1:
SIMCOP_IRQ1 is generated when VTNF_IRQ is generated:
Example 2:
SIMCOP_IRQ3 is generated when DMA_IRQ is generated:
To mask an interrupt for generation of the SIMCOP_IRQi output interrupts, software must clear the corresponding bit of the SIMCOP_HL_IRQENABLE_CLEAR_i (I = 0 to 3) register by setting it to 0.
When an event occurs, the corresponding bit in the SIMCOP_HL_IRQSTATUS_RAW_i (I = 0 to 3) register is set regardless of whether or not the event has been enabled. Bits in the SIMCOP_HL_IRQSTATUS_i (I = 0 to 3) registers are only set when an enabled event occurs. Software can clear a pending event by setting the appropriate bit in the SIMCOP_HL_IRQSTATUS_i (I = 0 to 3) register.