SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Address Offset | See Table 16-145 | ||
Physical Address | 0x4480 3500 0x4480 3600 0x4500 0200 | Instance | CLK1_FLAGMUX_CLK1_1 CLK1_FLAGMUX_CLK1_2 CLK2_FLAGMUX_CLK2_1 |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STDHOSTHDR_COREREG_CORECODE | RESERVED | STDHOSTHDR_COREREG_VENDORCODE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:22 | RESERVED | Reserved | R | 0x000 |
21:16 | STDHOSTHDR_COREREG_CORECODE | The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37. | R | 0x37 |
15:1 | RESERVED | Reserved | R | 0x0000 |
0 | STDHOSTHDR_COREREG_VENDORCODE | The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1. | R | 1 |
Read 0x0: Third-party vendor. | ||||
Read 0x1: |
L3_MAIN Interconnect |
Address Offset | See Table 16-145 | ||
Physical Address | 0x4480 3504 0x4480 3604 0x4500 0204 | Instance | CLK1_FLAGMUX_CLK1_1 CLK1_FLAGMUX_CLK1_2 CLK2_FLAGMUX_CLK2_1 |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STDHOSTHDR_VERSIONREG_REVISIONID | STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | STDHOSTHDR_VERSIONREG_REVISIONID | The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0. | R | 0x00 |
23:0 | STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM | Reserved. Type: Reserved. Reset value: Reserved. | R | 0x000000 |
L3_MAIN Interconnect |
Address Offset | See Table 16-145 | ||
Physical Address | 0x4480 3508 0x4480 3608 0x4500 0208 | Instance | CLK1_FLAGMUX_CLK1_1 CLK1_FLAGMUX_CLK1_2 CLK2_FLAGMUX_CLK2_1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
MASK0 |
L3_MAIN Interconnect |
Address Offset | See Table 16-145 | ||
Physical Address | 0x4480 350C 0x4480 360C 0x4500 020C | Instance | CLK1_FLAGMUX_CLK1_1 CLK1_FLAGMUX_CLK1_2 CLK2_FLAGMUX_CLK2_1 |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
REGERR0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REGERR0 | Flag inputs 0 Type: Status. Reset value: X. | R | 0x00000 |
L3_MAIN Interconnect |
Address Offset | See Table 16-145 | ||
Physical Address | 0x4480 3510 0x4480 3610 0x4500 0210 | Instance | CLK1_FLAGMUX_CLK1_1 CLK1_FLAGMUX_CLK1_2 CLK2_FLAGMUX_CLK2_1 |
Description | |||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASK1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | MASK1(1) | Mask flag inputs 1 Type: Control. Reset value: 0x7FFFFF. | RW | See (2) |
L3_MAIN Interconnect |
Address Offset | See Table 16-145 | ||
Physical Address | 0x4480 3514 0x4480 3614 0x4500 0214 | Instance | CLK1_FLAGMUX_CLK1_1 CLK1_FLAGMUX_CLK1_2 CLK2_FLAGMUX_CLK2_1 |
Description | |||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REGERR1 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REGERR1 | Flag inputs 1 Type: Status. Reset value: X. | R | 0x00000 |
L3_MAIN Interconnect |